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CHAPTER 16 INTERRUPT FUNCTION
User’s Manual U15017EJ2V0UD
16.1 Interrupt Request Sources
The
μ
PD784975A has the 23 interrupt request sources shown in Table 16-2, with a vector table allocated to each.
Table 16-2. Interrupt Request Sources (1/2)
Interrupt
Request
Default
Priority
Interrupt Request
Generating Source
Generating
Unit
Interrupt
Control
Context
Switching
Register
Name
Macro
Service
Macro
Service
Control
Word
Address
Vector
Table
Address
Software
None
BRK instruction execution
—
—
Not
possible
Not
possible
—
003EH
BRKCS instruction execution
—
—
Possible
Not
possible
—
—
Operand
error
None
Invalid operand in MOV STBC,
#byte instruction or MOV WDM,
#byte instruction, and LOCATION
instruction
—
—
Not
possible
Not
possible
—
003CH
Non-
maskable
None
INTWDT (watchdog timer
overflow)
Watchdog
timer
—
Not
possible
Not
possible
—
0004H
Maskable
0
INTWDTM (watchdog timer
overflow)
WDTIC
Possible
Possible
0FE06H
0006H
1
INTP0 (pin input edge detection)
Edge
detection
PIC0
0FE08H
0008H
2
INTP1 (pin input edge detection)
PIC1
0FE0AH
000AH
3
INTP2 (pin input edge detection)
PIC2
0FE0CH
000CH
4
INTTM00 (occurrence of signal
indicating a match between the
16-bit timer counter (TM0) and
capture compare register (CR00))
16-bit
timer/event
counter 0
TMIC00
0FE0EH
000EH
5
INTTM01 (occurrence of signal
indicating a match between the
16-bit timer counter (TM0) and
capture compare register (CR01))
TMIC01
0FE10H
0010H
6
INTKS (timing of key scanning
from VFD controller/driver)
VFD controller/
KSIC
0FE12H
0012H
driver
7
INTCSI0 (end of 3-wire transfer
of CSI0)
Serial
interface
CSIIC0
0FE14H
0014H
8
INTCSI1 (end of 3-wire transfer
of CSI1)
CSIIC1
0FE16H
0016H
9
INTTM50 (match between the 8-bit 8-bit PWM
timer counter (TM50) and 8-bit
compare register (CR50))
TMIC50
0FE18H
0018H
timer
(TM50)
10
INTTM51 (match between the 8-bit 8-bit PWM
timer counter (TM51) and 8-bit
compare register (CR51))
TMIC51
0FE1AH
001AH
timer
(TM51)
11
INTAD (end of A/D conversion)
A/D converter
ADIC
0FE1CH
001CH
Remarks 1.
The default priority is a fixed number. This indicates the order of priority when interrupt requests
specified as having the same priority are generated simultaneously.
CSI: Clocked synchronous serial interface
2.