
218
User
’
s Manual U15017EJ2V0UD
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE
(d) Reception
When the RXE0 bit of the asynchronous serial interface mode register 0 (ASIM0) is set to 1, reception is
enabled and sampling of the RxD0 pin input is performed.
Sampling of the RxD0 pin input is performed by the serial clock set in ASIM0.
When the RxD0 pin input becomes low level, the 5-bit counter of the port rate generator starts counting, and
outputs the data sampling start timing signal when half the time of the set baud rate has elapsed. If the result
of re-sampling the RxD0 pin input with this start timing signal is low level, the RxD0 pin input is perceived
as the start bit, the 5-bit counter is initialized and begins counting, and data sampling is performed. When,
following the start bit, character data, the parity bit, and one stop bit are detected, reception of one frame
of data is completed.
When reception of one frame of data is completed, the receive data in the shift register is transferred to the
receive shift register (RXB0), and a receive completion interrupt (INTSR0) is generated.
Moreover, even if an error occurs, the receive data for which the error occurred is transferred to RXB0. If
an error occurs, when bit 1 (ISRM0) of ASIM0 is cleared to 0, INTSR0 is generated. (refer to
Figure 13-
9
).
When bit ISRM0 is set to 1, INTSR0 is not generated.
When bit RXE0 is reset to 0 during a receive operation, the receive operation is immediately stopped. At
this time, the contents of RXB0 and ASIS0 remain unchanged, and INTSR0 and INTSER0 are not generated.
Figure 13-8. Asynchronous Serial Interface Receive Completion Interrupt Timing
Caution
Even when a receive error occurs, be sure to read the receive buffer register 0 (RXB0).
If RXB0 is not read, an overrun error will occur during reception of the next data, and
the reception error status will continue indefinitely.
STOP
Parity
D7
D6
D2
D1
D0
START
RxD0 (input)
INTSR0