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CHAPTER 3 CPU ARCHITECTURE
User
’
s Manual U15017EJ2V0UD
3.4 Internal Data Area
The internal data space consists of the internal RAM area and the special function register area (refer to
Figures
3-1
and
3-2
).
The final address in the internal data area can be set to 0FFFFH (when executing the LOCATION 0H instruction)
or FFFFFH (when executing the LOCATION 0FH instruction) by the LOCATION instruction. The address selection
of the internal data area by this LOCATION 0H must be executed once immediately after a reset is cleared. After
one selection, updating is not possible. The program following a reset clear must be as shown in the example. If
the internal data area and another area are allocated to the same address, the internal data area becomes the access
target, and the other area cannot be accessed.
Example
RSTVCT
CSEG AT 0
DW
RSTSTRT
INITSEG
CSEG BASE
RSTSTRT:
LOCATION 0H ; or LOCATION 0FH
MOVG SP, #STKBGN
MOV MM, #80H
Caution When the LOCATION 0H instruction is executing, the program after clearing the reset must not
overlap the internal data area. In addition, make sure the entry address of the servicing routine
for a non-maskable interrupt does not overlap the internal data area. The entry area for a
maskable interrupt must be initialized before referencing the internal data area.
3.4.1 Internal RAM area
The
μ
PD784975A has an on-chip general-purpose static RAM.
This space has the following configuration.
Peripheral RAM (PRAM)
Internal RAM area
Internal high-speed RAM (IRAM)
Table 3-2. Internal RAM Area List
Internal RAM
Internal RAM Area
Part Number
Peripheral RAM: PRAM
Internal High-speed RAM: IRAM
μ
PD784975A
3,584 bytes
(0F100H to 0FEFFH)
3,072 bytes
(0F100H to 0FCFFH)
512 bytes
(0FD00H to 0FEFFH)
μ
PD78F4976A
5,120 bytes
(0EB00H to 0FEFFH)
4,608 bytes
(0EB00H to 0FCFFH)
Remark
The addresses in the table are the values when the LOCATION 0H instruction is executing. When
the LOCATION 0FH instruction is executing, 0F0000H is added to the above values.
to