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CHAPTER 17 STANDBY FUNCTION
User
’
s Manual U15017EJ2V0UD
17.7 Cautions
(1) If the HALT/STOP/IDLE mode (standby mode hereafter) setting is performed when a condition that release the
HALT mode (refer to
17.3.2 HALT mode release
) is satisfied, standby mode is not entered, and execution of
the next instruction, or a branch to a vectored interrupt service program, is performed. To ensure that a definite
standby mode setting is made, interrupt requests should be cleared, etc. before entering the standby mode.
(2) When crystal/ceramic oscillation is used, the EXTC bit must be cleared (to 0) before use. If the EXTC bit is set
(to 1), oscillation will stop.
(3) When the STOP mode is used in a system that uses an external clock, the EXTC bit of OSTS must be set (to
1). If STOP mode setting is performed in a system to which an external clock is input when the EXTC bit of OSTS
is cleared (to 0), the current consumption increases.
When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock input to
the X1 pin, to the X2 pin (refer to
5.4 Main System Clock Oscillator
).
(4) In the STOP and IDLE modes, the ADCS bit of the A/D converter mode register (ADM) should be cleared (to
0).
(5) Execute an NOP instruction three times after the standby instruction (after the standby mode has been released).
Otherwise, the standby instruction cannot be executed if execution of the standby instruction and an interrupt
request contend, and the interrupt is acknowledged after two or more instructions following the standby instruction
have been executed. The instruction that is executed before acknowledging the interrupt is the one that is
executed within up to 6 clocks after the standby instruction has been executed.
Example
MOV STBC, #byte
NOP
NOP
NOP
…