
264
CHAPTER 16 INTERRUPT FUNCTION
User
’
s Manual U15017EJ2V0UD
Figure 16-14. Examples of Servicing When Another Interrupt Request Is Generated During
Interrupt Service (3/3)
Notes 1.
Low default priority
2.
High default priority
Remarks 1.
“
a
”
to
“
z
”
in the figure above are arbitrary names used to differentiate between the interrupt requests
and macro service requests.
High/low default priorities in the figure indicate the relative priority levels of the two interrupt
requests.
2.
Main routine
EI
EI
EI
EI
EI
EI
Interrupt request q
(Level 3)
Interrupt request u
(Level 0)
w macro service
q servicing
r servicing
s servicing
t servicing
u servicing
v servicing
x servicing
y servicing
z servicing
Interrupt request x
(Level 1)
Interrupt
request t
(Level 0)
<1>
<2>
<4>
Note 2
Multiple acknowledgment of levels 3 to 0. If
the PRSL bit of the IMC register is set (1),
only macro service requests and non-
maskable interrupts generate nesting
beyond this.
If the PRSL bit of the IMC register is
cleared (0), level 3 interrupts can also be
nested during level 3 interrupt servicing
(refer to
Figure 14-16
).
<1>: Interrupt request v (level 0)
<2>: Macro service interrupt w (level 3)
Even though the interrupt enabled state is
set during servicing of level 0 interrupt
request u, the interrupt request is not
acknowledged but held pending even
though its priority is 0. However, the
macro service request is acknowledged
and serviced irrespective of its level and
even though there is a pending interrupt
with a higher priority level.
<3>: Interrupt request y (level 2)
<4>: Interrupt request z (level 2)
Pending interrupt requests y and z are
acknowledged after servicing of interrupt
request x. As interrupt requests y and z
have the same priority level, interrupt
request z which has the higher default
priority is acknowledged first, irrespective
of the order in which the interrupt requests
were generated.
Interrupt
request r
(Level 2)
Interrupt
request s
(Level 1)
<3>
Note 1