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CHAPTER 3 CPU ARCHITECTURE
User
’
s Manual U15017EJ2V0UD
3.5
μ
PD78F4976A Memory Mapping
The
μ
PD78F4976A has a 128 KB flash memory and 5,120-byte internal RAM.
The
μ
PD78F4976A has a function (memory size switching function) so that a part of the internal memory is not
used by the software.
The memory size is switched by the internal memory size switching register (IMS).
Based on the IMS setting, the memory mapping can be the same memory mapping as the mask ROM products
with different internal memories (ROM, RAM).
IMS can only be written by an 8-bit memory manipulation instruction.
RESET input sets IMS to FFH.
Figure 3-5. Format of Internal Memory Size Switching Register (IMS)
Address: 0FFFCH After reset: FFH W
Symbol
7
6
5
4
3
2
1
0
IMS
1
1
ROM1
ROM0
1
1
RAM1
RAM0
ROM1
ROM0
Internal ROM capacity selection
0
0
Setting prohibited
0
1
Setting prohibited
1
0
96 KB
1
1
128 KB
RAM1
RAM0
Internal RAM capacity selection
Note
0
0
Setting prohibited
0
1
3,584 bytes
1
0
Setting prohibited
1
1
5,120 bytes
Note
The internal RAM capacity is the sum of the peripheral RAM capacity and high-speed RAM capacity.
Cautions 1.
The mask ROM version (
μ
PD784975A) does not have an IMS.
Even if the IMS write instruction is executed in the mask ROM version, it does not have
any effect on operations.
In the case that the
μ
PD78F4976A is selected as the emulation CPU in the in-circuit
emulator, the memory size would always be
“
FFH
”
even if a write instruction other than
FFH is executed to IMS.
2.
Table 3-3 shows the IMS settings that have the same memory map as the mask ROM version.
Table 3-3. Settings of the Internal Memory Size Switching Register (IMS)
Target Mask ROM Version
IMS Setting
μ
PD784975A
EDH