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CHAPTER 16 INTERRUPT FUNCTION
User
’
s Manual U15017EJ2V0UD
16.9 When Interrupt Requests and Macro Service Are Temporarily Held Pending
When the following instructions are executed, interrupt acknowledgment and macro service processing is pending
for 8 system clock cycles. However, software interrupts are not deferred.
EI
DI
BRK
BRKCS
RETCS
RETCSB !addr16
RETI
RETB
LOCATION 0H or LOCATION 0FH
POP PSW
POPU post
MOV PSWL, A
MOV PSWL, #byte
MOVG SP, #imm24
Write instruction and bit manipulation instruction (excluding BT and BF) to interrupt control registers
Note
, MK0,
MK1L, IMC, and ISPR.
PSW bit manipulation instruction
(Excluding the BT PSWL.bit, $addr20 instruction, BF PSWL.bit, $addr20 instruction, BT PSWH.bit, $addr20
instruction, BF PSWH.bit, $addr20 instruction, SET1 CY instruction, NOT1 CY instruction, and CLR1 CY
instruction)
Note
Interrupt control registers: WDTIC, PIC0, PIC1, PIC2, TMIC00, TMIC01, KSIC, CSIIC0, CSIIC1, TMIC50,
TMIC51, ADIC, REMIC, CSIIC2, SERIC0, SRIC0, STIC0, WTIIC, WTIC
Caution If problems are caused by a long pending period for interrupts and macro service when the
instructions to be applied are used in succession, insert an instruction such as NOP to create
a timing that can receive interrupts and macro service requests without leaving them pending.
16.10 Instructions Whose Execution Is Temporarily Suspended by an Interrupt or Macro Service
Execution of the following instructions is temporarily suspended by an acknowledgeable interrupt request or macro
service request, and the interrupt or macro service request is acknowledged. The suspended instruction is resumed
after completion of the interrupt service program or macro service processing.
Temporarily suspended instructions:
MOVM, XCHM, MOVBK, XCHBK
CMPME, CMPMNE, CMPMC, CMPMNC
CMPBKE, CMPBKNE, CMPBKC, CMPBKNC
SACW