
43
CHAPTER 1 OUTLINE
User
’
s Manual U14701EJ3V0UD
1.7 Outline of Functions
(1/2)
Part Number
μ
PD780316
μ
PD780318
μ
PD780326
μ
PD780328
μ
PD780336
μ
PD780338
μ
PD78F0338
Item
Internal
memory
ROM
48 KB
(mask ROM)
60 KB
(mask ROM)
48 KB
(mask ROM)
60 KB
(mask ROM)
48 KB
(mask ROM)
60 KB
(mask ROM)
60 KB
Note
(flash
memory)
High-speed RAM
1,024 bytes
Expansion RAM
1,536 bytes
LCD display RAM
40
×
8 bits
Memory space
64 KB
General-purpose registers
8 bits
×
32 registers (8 bits
×
8 registers
×
4 banks)
Minimum instruction execution time
Function to change minimum instruction execution time provided
When main system
clock selected
0.2
μ
s/0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s (@V
DD
= 5 V, f
X
= 10 MHz)
When subsystem
clock selected
122
μ
s (@f
XT
= 32.768 kHz)
Instruction set
16-bit operation
Multiply/divide (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulate (set, reset, test, and Boolean operation)
BCD adjust, etc.
I/O ports
70
62
54
70
CMOS input
8
CMOS output
16
8
None
16 (alternate
with segment
pin)
CMOS I/O
42
N-ch open-drain I/O (15 V)
4
A/D converter
10-bit resolution
×
10 channels
Low-voltage operation: AV
REF0
= 1.8 to 5.5 V
D/A converter
8-bit resolution
×
1 channel
LCD controller/driver
LCD reference voltage generator: booster type (
×
3 only)
Fine tuning of LCD reference voltage possible with external resistor
Blinking display possible (blinking interval can be selected: 0.5 s or 1 s)
Static display and dynamic display (1/3 bias only) can be used simultaneously
(Static display up to 12 segments)
Segment signal output
24 max.
32 max.
40 max.
40 max.
(when alter-
nate with port
pins: 16)
Common signal output
4 max. (dynamic display), 1 (static display)
Note
The capacity of the internal flash memory can be changed by means of the memory size switching register
(IMS).