22
User’s Manual U14701EJ3V0UD
LIST OF FIGURES (6/7)
Figure No.
Title
Page
18-5
External Interrupt Rising Edge Enable Register (EGP),
External Interrupt Falling Edge Enable Register (EGN) Format ..........................................................
313
18-6
Program Status Word Format ..............................................................................................................
314
18-7
Non-Maskable Interrupt Request Generation to Acknowledge Flowchart ...........................................
316
18-8
Non-Maskable Interrupt Request Acknowledge Timing .......................................................................
316
18-9
Non-Maskable Interrupt Request Acknowledge Operation ..................................................................
317
18-10
Interrupt Request Acknowledge Processing Algorithm........................................................................
319
18-11
Interrupt Request Acknowledge Timing (Minimum Time) ....................................................................
320
18-12
Interrupt Request Acknowledge Timing (Maximum Time) ...................................................................
320
18-13
Nesting Examples ................................................................................................................................
322
18-14
Interrupt Request Hold.........................................................................................................................
324
19-1
Oscillation Stabilization Time Select Register (OSTS) Format ............................................................
326
19-2
HALT Mode Release by Interrupt Request Generation........................................................................
328
19-3
HALT Mode Release by RESET Input .................................................................................................
329
19-4
STOP Mode Release by Interrupt Request Generation.......................................................................
331
19-5
STOP Mode Release by RESET Input ................................................................................................
332
20-1
Reset Function Block Diagram ............................................................................................................
333
20-2
Timing of Reset by RESET Input .........................................................................................................
334
20-3
Timing of Reset Due to Watchdog Timer Overflow ..............................................................................
334
20-4
Timing of Reset in STOP Mode by RESET Input.................................................................................
334
21-1
ROM Correction Block Diagram...........................................................................................................
337
21-2
Correction Address Registers 0 and 1 Format.....................................................................................
338
21-3
Correction Control Register (CORCN) Format ....................................................................................
339
21-4
Storing Example to EEPROM (When One Place Is Corrected)...........................................................
340
21-5
Initialization Routine.............................................................................................................................
341
21-6
ROM Correction Operation ..................................................................................................................
342
21-7
ROM Correction Example ....................................................................................................................
343
21-8
Program Transition Diagram (When One Place Is Corrected) .............................................................
344
21-9
Program Transition Diagram (When Two Places Are Corrected) .........................................................
345
22-1
Memory Size Switching Register (IMS) Format ...................................................................................
348
22-2
Internal Expansion RAM Size Switching Register (IXS) Format..........................................................
349
22-3
Environment for Writing Program to Flash Memory .............................................................................
350
22-4
3-Wire Serial I/O (SIO3).......................................................................................................................
351
22-5
3-Wire Serial I/O (CSI1) .......................................................................................................................
351
22-6
UART (UART0) ....................................................................................................................................
352
22-7
V
PP
Pin Connection Example ...............................................................................................................
353