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CHAPTER 17 LCD CONTROLLER/DRIVER
User’s Manual U14701EJ3V0UD
Table 17-2 shows the maximum number of pixels that can be displayed in each display mode.
Table 17-2. Maximum Number of Pixels Displayed
Part Number
Bias Mode
Time Division
Common Signals
Maximum Number of Pixels
μ
PD780316, 780318, 78F0338
—
Static
SCOM0
12 (12 segment
×
1 common)
1/3
3
COM0 to COM2
72 (24 segment
×
3 common)
4
COM0 to COM3
96 (24 segment
×
4 common)
μ
PD780326, 780328
—
Static
SCOM0
12 (12 segment
×
1 common)
1/3
3
COM0 to COM2
96 (32 segment
×
3 common)
4
COM0 to COM3
128 (32 segment
×
4 common)
μ
PD780336, 780338
—
Static
SCOM0
12 (12 segment
×
1 common)
1/3
3
COM0 to COM2
120 (40 segment
×
3 common)
4
COM0 to COM3
160 (40 segment
×
4 common)
17.2 LCD Controller/Driver Configuration
The LCD controller/driver consists of the following hardware.
Table 17-3. LCD Controller/Driver Configuration
Item
Configuration
Display output
μ
PD780316, 780318
Segment signal:
24 lines
Dynamic/static alternated: 12 lines
Dynamic display segment: 12 lines
4 lines (for dynamic display)
1 line (for static display)
Common signal:
μ
PD780326, 780328
Segment signal:
32 lines
Dynamic/static alternated: 12 lines
Dynamic display segment: 20 lines
4 lines (for dynamic display)
1 line (for static display)
Common signal:
μ
PD780336, 780338
Segment signal:
40 lines
Dynamic/static alternated: 12 lines
Dynamic display segment: 28 lines
4 lines (for dynamic display)
1 line (for static display)
Common signal:
μ
PD78F0338
Segment signal:
40 lines
Dynamic/static alternated: 12 lines
Dynamic display segment: 12 lines
Segment/output port:
4 lines (for dynamic display)
1 line (for static display)
16 lines
Common signal:
Control register
LCD display mode register 3 (LCDM3)
LCD clock control register 3 (LCDC3)
Static/dynamic display switching register 3 (SDSEL3)
Pin function switching register 8 (PF8)
Note
Pin function switching register 9 (PF9)
Note
Note
μ
PD78F0338 only