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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 4
User
’
s Manual U14701EJ3V0UD
(1) 16-bit timer mode control register 4 (TMC4)
This register controls the 16-bit timer counter 4 (TM4) count operation and timer output (TO4), selects the
operation mode, specifies the TO4 initial value, and sets the TM4 count clock and valid edge of TI4 input.
TMC4 is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the value of this register to 00H.
Figure 7-2. 16-Bit Timer Mode Control Register 4 (TMC4) Format
TCE4
TM4 count operation control
0
Count operation stop (TM4 cleared to 0)
1
Count operation start
TMM4
TM4 operation mode selection
INTTM4 generation timing
0
Clear & start on match between TM4 and
CR4
Note 2
Match between TM4 and CR4
1
Free-running mode
INTTM4 not generated
TMO4
Timer output (TO4) control
0
Output disabled (output level is fixed at 0)
1
Output enabled
LVS4
Timer output (TO4) initial value setting
0
Low level
1
High level
OVF4
The value of OVF4 reversed each time an overflow occurs (reset value: OVF4 = 0).
TCL41
TCL40
Count clock selection
0
0
f
X
(10 MHz)
0
1
f
X
/2
5
(312.5 kHz)
1
0
f
X
/2
7
(78.125 kHz)
1
1
Rising edge of TI4
Notes 1.
Bit 3 is a read-only bit.
2.
Overflow is not detected if clear & start mode is selected by match between TM4 and CR4.
Caution Be sure to stop timer operation (TCE4 = 0) before setting TMC4.
Remarks 1.
The initial value of TO4 is the timer output value of TO4 when timer output is enabled
(TMO4 = 1) and the count operation is stopped (TCE4 = 0).
2.
f
X
: Main system clock oscillation frequency
3.
Figures in parentheses are for operation with f
X
= 10 MHz.
7
TCE4
Symbol
TMC4
6
TMM4
5
TMO4
4
LVS4
3
OVF4
2
0
1
TCL41
0
TCL40
Address: FF68H After reset: 00H R/W
Note 1