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APPENDIX F REVISION HISTORY
User’s Manual U14701EJ3V0UD
(2/3)
Edition
Contents
Applied to:
2nd edition
Deletion of infrared data transfer mode in
CHAPTER 14 SERIAL INTERFACE UART0 CHAPTER 14
SERIAL
INTERFACE
UART0
Change of description in
16.4.2 3-wire serial I/O mode (3) Communication
operation
CHAPTER 16
SERIAL
INTERFACE CSI1
Change of
Figure 16-4 Timing in 3-Wire Serial I/O Mode
Change of
Figure 16-6 Output Operation of First Bit
Change of
Figure 16-7 Output Value of SO1 Pin (Last Bit)
Addition of
Figure 17-5 Relationship Between Reference Clock Generating Frame
Frequency, and Frame Frequency
CHAPTER 17 LCD
CONTROLLER/
DRIVER
Addition of
Caution
to
Figure 18-2 Interrupt Request Flag Registers (IF0L, IF0H,
IF1L) Format
CHAPTER 18
INTERRUPT
FUNCTIONS
Addition of
22.3 Flash Memory Characteristics
CHAPTER 22
μ
PD78F0338
Addition of
CHAPTER 24 ELECTRICAL SPECIFICATIONS
CHAPTER 24
ELECTRICAL
SPECIFICATIONS
Addition of
CHAPTER 25 PACKAGE DRAWINGS
CHAPTER 25
PACKAGE
DRAWINGS
Addition of
CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS
CHAPTER 26
RECOMMENDED
SOLDERING
CONDITIONS
Change of
APPENDIX B DEVELOPMENT TOOLS
APPENDIX B
DEVELOPMENT
TOOLS
Change of
APPENDIX C EMBEDDED SOFTWARE
APPENDIX C
EMBEDDED
SOFTWARE
Addition of
APPENDIX D NOTES ON DESIGNING TARGET SYSTEM
APPENDIX D
NOTES ON
DESIGNING
TARGET SYSTEM
3rd edition
Change of Recommended Connection of Unused Pins for the following pins in
Table 2-1 Pin I/O Circuit Types
P60 to P63
P80/S32 to P87/S39 (for flash memory version)
P90/S24 to P97/S31 (for flash memory version)
CHAPTER 2
PIN FUNCTIONS
Addition of description to
(1) Internal high-speed RAM
and
(2) Internal expansion
RAM
in
3.1.2 Internal data memory space
CHAPTER 3 CPU
ARCHITECTURE
Change of Manipulatable Bit Unit for ports 8 and 9 in
Table 3-4 Special Function
Register List