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CHAPTER 20 RESET FUNCTION
User
’
s Manual U14701EJ3V0UD
Table 20-1. Hardware Statuses After Reset (2/2)
Hardware
Status After Reset
Watch timer
Operation mode register 0 (WTNM0)
00H
Watchdog timer
Clock select register (WDCS)
00H
Mode register (WDTM)
00H
Clock output/buzzer output
controller
Clock output select register (CKS)
00H
A/D converter
Conversion result register 0 (ADCR0)
00H
Mode register 0 (ADM0)
00H
Analog input channel specification register 0 (ADS0)
00H
D/A converter
Conversion value setting register 0 (DA0)
00H
Mode register 0 (DAM0)
00H
Serial interface UART0
Asynchronous serial interface mode register 0 (ASIM0)
00H
Asynchronous serial interface status register 0 (ASIS0)
00H
Baud rate generator control register 0 (BRGC0)
00H
Transmit shift register 0 (TXS0)
FFH
Receive buffer register 0 (RXB0)
Serial interface CSI1
Shift register 1 (SIO1)
Undefined
Transmit buffer register 1 (SOTB1)
Undefined
Operation mode register 1 (CSIM1)
00H
Clock select register 1 (CSIC1)
10H
Serial interface SIO3
Shift register 3 (SIO3)
Undefined
Operation mode register 3 (CSIM3)
00H
LCD controller/driver
Operation/display mode register 3 (LCDM3)
00H
Clock control register 3 (LCDC3)
00H
Static/dynamic display switching register 3 (SDSEL3)
00H
Interrupt
Request flag registers 0L, 0H, 1L (IF0L, IF0H, IF1L)
00H
Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L)
FFH
Priority specification flag registers 0L, 0H, 1L
(PR0L, PR0H, PR1L)
FFH
External interrupt rising edge enable register (EGP)
00H
External interrupt falling edge enable register (EGN)
00H
ROM correction
Correction address registers 0, 1 (CORAD0, CORAD1)
0000H
Correction control register (CORCN)
00H