參數(shù)資料
型號： PCA5007
廠商： NXP Semiconductors N.V.
英文描述： Pager baseband controller
中文描述： 傳呼機基帶控制器
文件頁數(shù)： 98/112頁
文件大小： 604K
代理商： PCA5007
1998 Oct 07
98
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Fig.61 Parallel programming mode.
handbook, full pagewidth
MGR164
PROGRAMMER
LS0
LS1
PGM
RdStrb
GBMbpB
WEB
ADDL/ADDH/DATA I/O
PCA5007
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P0.0 to P0.7
SIG
SEC
MIN
PSEN
ALE
EA
MOUT2
MOUT1
RESETN
VDD
RESETIN
VDD, VDDA, VDD(DC), VBAT
VSS, VSSA, VSS(DC)
CLOCK
TCLK, XTL1
VSS
VPP
VPP
15.3
Entering the parallel programming mode
The parallel programming mode has been implemented as
a general test mode of the PCA5007. This mode can be
entered by applying 000 to pins PSEN, ALE and EA during
reset. For the initializing sequence a clock of 76.8 kHz at
XTL1 is expected and the supply voltage V
DD
must be
higher then 2.2 V. At the rising edge of RESOUT these
signals are latched and the code 000 leads to parallel
programming mode. The high voltage pin V
PP
can be
either HIGH or V
DD
.
Since PSEN and ALE are output signals of the PCA5007
after reset, a pull-down (strong enough to overdrive the
internal 100
μ
A pull-up of the PCA5007) should be used to
drive the outputs LOW. Alternatively the LOW can be
driven with a 3-state buffer which is enabled with
RESOUT = LOW.
The microcontroller fetches instructions from Port 0 in
external mode. Data fetching is controlled by PSEN and
ALE. This is the standard data fetch in external mode.
A clock has to be supplied to TCLK while entering the
parallel programming mode. Before entering the parallel
programming mode, Port 2 should be set to 30H and the
microcontroller should be put in Idle mode by setting the bit
PCON.0 (address 87H).
The test mode is activated by making EA equal to logic 1.
The mode entering sequence is given in Table 65.
Before entering the parallel program mode Port 2 can be
an output port (dependent on the reset configuration of this
port). As soon as the parallel programmed mode is entered
Port 2 is an input.
After entering the parallel programming mode this mode
has to be initialized. The OTP test latch has to be loaded
with code 01H to set the sense amplifiers in verify mode.
Before a byte can be programmed a verify has to be
performed to ensure that the programming is not blocked
by the security (see Section 15.10). The address of this
verify cycle is not important and the address latches do not
have to be loaded. After this initialization the PCA5007 is
ready for programming. Parallel program mode
initialization is shown in Fig.64.
The security check can be replaced by another read action
e.g. reading the security or signature bytes
(see Section 15.9).
It should be noted that this paragraph is only
applicable for the first series. It can be neglected in the
future.
To prevent problems with the self timed loop it is
advised to set the circuit in DC read mode during verify.
This is achieved by writing 09H instead of 01H into the
OTP test latch.
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