1998 Oct 07
53
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
6.19.6
P
ORT
1
INTERRUPTS
: P
ORT
1.0
TO
P
ORT
1.4
(INT2
TO
INT6)
Four Port 1 lines can be used as external interrupt inputs
(see Fig.25). When enabled (IEN1 SFR), each of these
lines can wake-up the device from power-down. Using the
IX1 register, each of these port lines may be set active to
either HIGH or LOW. IRQ1 is the interrupt request flag
register. Each flag, if the interrupt is enabled, will send an
interrupt request, but must be cleared by software, i.e. via
the interrupt software. The Port 1 interrupt request flags
can only be set if the corresponding interrupt enable bit is
set.
6.19.7
M
ORE INTERRUPTS
: S
YM
C
LK
, DC/DC
CONVERTER
,
WATCHDOG AND MINUTE
The decoder blocks generate events that can force an
interrupt when enabled (IEN0 and IEN1 SFR). These
interrupts are mapped to the corresponding P1 interrupt
request flag register bits (see Fig.26). Each flag, if the
interrupt is enabled, will send an interrupt request and
must be cleared by software, i.e. via the interrupt service
routine.
The IRQ bits are not set if the corresponding enable is not
set.
IRQ1.3:
(symbol interrupt); this interrupt request flag, if
enabled, is set if the demodulator (clock recovery) has
data ready, that should be read by the microcontroller.
The event is called symbol clock or SymClk, because in
one mode of operation one symbol is delivered per
interrupt. The flag is set by hardware and needs to be
cleared by software.
IRQ1.5:
(DC/DC converter interrupt); this interrupt
request flag, if enabled, is set if the DC/DC converter is
not able to deliver the required current (STB flag
cleared). The flag is set by hardware and needs to be
cleared by software.
IRQ1.6:
(watchdog interrupt); this interrupt request flag,
if enabled, is set if the watchdog timer will expire within
1
16
s. The flag is set by hardware and needs to be
cleared by software.
IRQ1.7:
(minute interrupt); this interrupt request flag, if
enabled, is set once each minute by the real-time clock.
The flag is set by hardware and needs to be cleared by
software.
Fig.25 Interrupt Port 1.0.
handbook, full pagewidth
MGR128
IX1.0
INT2
X2
IEN1.0
IRQ1.0
wake-up.0
Pad Port 1.0
0
1
Fig.26 SymClk (as an example for any of the 4 mentioned interrupts).
handbook, full pagewidth
MGR129
IEN1.3
SymClk
CLOCK
RECOVERY
BLOCK
X5
IRQ1.3