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參數(shù)資料
| 型號： | PCA5007 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Pager baseband controller |
| 中文描述： | 傳呼機基帶控制器 |
| 文件頁數(shù)： | 47/112頁 |
| 文件大?。?/td> | 604K |
| 代理商： | PCA5007 |
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1998 Oct 07
47
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
6.19
Interrupt system
External events and the real-time-driven on-chip
peripherals require service by the CPU asynchronously to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. The interrupt system
is shown in Fig.27. The PCA5007 acknowledges interrupt
requests from fifteen sources as follows:
INT0 to INT4 and INT6
Timer 0 and Timer 1
Wake-up counter
I
2
C-bus serial I/O
UART transmitter and receiver
Demodulator
DC/DC converter
Watchdog timer
Real-time clock (MINUTE).
Each interrupt vectors to a separate location in program
memory for its service routine. Each source can be
individually enabled or disabled by its corresponding bit in
the Interrupt Enable Registers (IEN0 and IEN1).
The priority level is selected via the Interrupt Priority
Registers (IP0 and IP1). All enabled sources can be
globally disabled or enabled.
6.19.1
O
VERVIEW
The interrupt controller implemented in the PCA5007 has
15 interrupt sources, of which some are level sensitive and
some are edge sensitive. The interrupt controller samples
all active sources during one instruction cycle; evaluation
of the interrupts is then performed. A priority decoder
decides which interrupt is serviced. Each interrupt has its
own vector pointing to an 8 bytes long program segment.
A low priority interrupt can be interrupted by a high priority
interrupt, but not by another low priority interrupt i.e. only
two interrupt levels are possible. Between the RETI
instruction (Return from Interrupt) and the LCALL to a next
interrupt, there is at least one instruction of the lower
program level executed (see Fig.22).
An interrupt is performed with a long subroutine call
(LCALL) to vector address, which is determined by the
respective interrupt. During LCALL the PC is pushed onto
the stack. Returning from interrupt with RETI, the PC is
popped from the stack.
Fig.22 Interrupt hierarchy.
handbook, full pagewidth
MGR125
Interrupt level 2x
Interrupt level 1
Program level 0
RETI
Level 21
RETI
Level 20
RETI
one
instruction
IP = 1
IP = 1
IP = 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCA5007H | Pager baseband controller |
| PCA5010 | Pager baseband controller |
| PCA5010H | Pager baseband controller |
| PCA82C200 | STAND-ALONE CAN-CONTROLLER |
| PCA82C200P | STAND-ALONE CAN-CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCA5007H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Pager baseband controller |
| PCA5007H/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| PCA5010 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Pager baseband controller |
| PCA5010H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Pager baseband controller |
| PCA5010H/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROCONTROLLER|8-BIT|8051 CPU|CMOS|QFP|48PIN|PLASTIC |
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