1998 Oct 07
38
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
6.14.2
W
AKE
-U
P
C
OUNTER
C
ONTROL
R
EGISTER
(WUCON)
The WUCON special function register is used to control the operation of the wake-up counter by software.
Table 30
Wake-up Counter Control Register (WUCON, SFR address 94H)
Table 31
Description of the WUCON bits
6.14.3
W
AKE
-U
P
D
ATA
R
EGISTERS
(WUC0, WUC1)
The WUC0 and WUC1 special function registers are used to define the interval to the next wake-up interrupt.
Table 32
Low Wake-UP Register (WUC0, SFR address 95H)
Table 33
High Wake-UP Register (WUC1, SFR address 96H)
7
6
5
4
3
2
1
0
RUN
WUP
TEST
CPL
Z1
Z0
LOAD
SET
BIT
SYMBOL
FUNCTION
WUCON.7
WUCON.6
RUN
WUP
Control signal from the processor.
Latched Wake-Up signal
. The bit is set by hardware (or software) and generates a
wake-up interrupt if enabled and the DC/DC STB bit is set. The bit needs to be cleared
by software (SFR and 1 V bits). A SET sequence is required to clear the flag on the 1 V
side. Attention: reading the bit reads the contents of the ‘real’ wake-up flag on the 1 V
side, (read/modify/write commands will fail on this bit).
Test control signal
(uses 76.8 kHz as clock input for high and low counter).
Set operation completed.
Bit set by hardware when the last operation is completed
and the SFRs are again ready to accept new settings. The bit generates a wake-up
interrupt if enabled. The bit needs to be cleared by software.
2 bits that are only reset by a primary RESETIN. The bits can be written to and read
from by the software. The bits are not cleared when the DC/DC converter is switched
off. Same procedure for setting the bits as WU0 to WU15 (reading these bits returns the
‘real’ flags on the 1 V side; read/modify/write commands will fail on this bit).
Load wake-up counter with contents of reload latch
(see Fig.19). Is sampled on the
positive edge of SET.
Clock signal for writing to RUN or wake-up SFR (on 1 V level).
WUCON.5
WUCON.4
TEST
CPL
WUCON.3
WUCON.2
Z1
Z0
WUCON.1
LOAD
WUCON.0
SET
7
6
5
4
3
2
1
0
WU7
WU6
WU5
WU4
WU3
WU2
WU1
WU0
7
6
5
4
3
2
1
0
WU15
WU14
WU13
WU12
WU11
WU10
WU9
WU8