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參數(shù)資料
| 型號： | PCA5007 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Pager baseband controller |
| 中文描述： | 傳呼機(jī)基帶控制器 |
| 文件頁數(shù)： | 41/112頁 |
| 文件大?。?/td> | 604K |
| 代理商： | PCA5007 |
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1998 Oct 07
41
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
SFR:
TFREQ0 to TFREQ7: 8-bit register containing the
divisor of the tone. Loaded by the processor.
ENB: Enable frequency generator. Control signal from
processor.
CLK2: Use secondary clock input for tone generation.
If set a 32768 Hz clock signal is generated from the
primary 76800 Hz clock signal and used as a timing
reference for the tone generator.
Inputs:
76.8 kHz: Input to the tone counter.
Outputs:
AT: Output for alerter. Is logic 0 when disabled:
TFREQ
6.15.3
G
ENERATION OF THE
32768 H
Z REFERENCE
The 32768 Hz reference is generated from 76800 Hz
according to the following algorithm:
forever do
begin
for 10 times do {
from 7 clocks on 76.8 kHz generate
3 pulses on 32 kHz
}
from 5 clocks on 76.8 kHz generate
2 pulses on 32 kHz
end
f
AT
76.8 kHz
=
6.16
Watchdog timer
6.16.1
F
UNCTION
The watchdog timer consists of an 8-bit down counter.
The binary number defined with WD3 to WD0 defines the
expiry time of the watchdog timer between 1 to 16 s. Once
enabled this counter is running continuously. Once expired
the timer produces firstly an interrupt and finally a reset.
The software must reload the watchdog in regular intervals
to avoid expiry.
A positive edge on the LD SFR bit (re)loads the counter
with the value of WD3 to WD0, sets the LOW bits to logic 1
and activates this counter if it is not yet running. However,
to prepare the (re)loading a positive edge must be applied
to the COND bit in WDCON. In this way at least two
locations in software must be passed before the counter
can be reloaded. After reset the counter is not running.
Only after the first LD it is clocked continuously by a clock
pulse of 16 Hz until the DC/DC converter is switched off or
an external reset is applied.
If the next LD signal is not given within the defined expiry
interval an overflow occurs and the processor will be reset
(signal WDR). A WDI interrupt is issued one clock cycle
before the reset is applied. This gives the opportunity to
avoid the reset if required. The maximum watchdog expiry
time is thus 254
×
16 Hz ticks to the WD interrupt and
255
×
16 Hz ticks to the reset.
If the DC/DC converter is in the off mode, the watchdog
timer is suspended.
6.16.2
W
ATCH
D
OG
T
IMER
C
ONTROL
R
EGISTER
(WDCON)
The WDCON special function register is used to control the operation of the on-chip watchdog timer.
Table 34
Watchdog Control Register (WDCON, SFR address A5H)
7
6
5
4
3
2
1
0
COND
WD3
WD2
WD1
WD0
LD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCA5007H | Pager baseband controller |
| PCA5010 | Pager baseband controller |
| PCA5010H | Pager baseband controller |
| PCA82C200 | STAND-ALONE CAN-CONTROLLER |
| PCA82C200P | STAND-ALONE CAN-CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCA5007H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Pager baseband controller |
| PCA5007H/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| PCA5010 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Pager baseband controller |
| PCA5010H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Pager baseband controller |
| PCA5010H/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROCONTROLLER|8-BIT|8051 CPU|CMOS|QFP|48PIN|PLASTIC |
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