參數(shù)資料
型號: PCA5007
廠商: NXP Semiconductors N.V.
英文描述: Pager baseband controller
中文描述: 傳呼機基帶控制器
文件頁數(shù): 103/112頁
文件大?。?/td> 604K
代理商: PCA5007
1998 Oct 07
103
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
15.7
High voltage timing
The external program voltage V
PP
has to be HIGH while a
program pulse is applied (WEB active). During verify it can
be either high or equal to the supply voltage. V
PP
has to be
stable for at least 10
μ
s before a program pulse can be
applied.
After applying a program pulse a recover time of 1
μ
s is
needed to discharge the internal high voltage nodes.
During this recover time the memory cannot be accessed
for verify.
Due to the above mentioned set-up time programming
time is reduced if V
PP
is continuously HIGH during
programming and verifying.
15.8
OTP test modes
OTP test modes will be selected from a test control latch
which can be loaded in parallel programming over Port 0.
The advantage of this is that the test modes of the OTP are
independent of the microcontroller. Table 66 shows the
OTP test modes coded in 7 bits. When a test mode is
loaded the control signals on Port 2 keep their original
functionality and can be used to execute the test mode.
Table 66
Definition of test modes
TCL(7 TO 0)
TEST MODE
00000000
XXXXXX01
XXXXXX10
XXXXXX11
XXXXX1XX
XXXX1XXX
X001XXXX
X010XXXX
X011XXXX
X100XXXX
X101XXXX
X110XXXX
X111XXXX
1XXXXXXX
normal mode (no test active)
verify mode (self timed)
margin 0 mode
margin 1 mode
margin VP mode is active
DC_Read mode is active
drain stress test mode
gate stress test mode
mass programming test mode
even column test mode
odd column test mode
even row test mode
odd row test mode
OTP interface test
The encoding is such that combinations of test modes are
possible, for instance TCB(7 to 0) = 00001100 enables
both the margin VP and DC_Read test modes.
The so called vt mode, needed to measure analog cell
characteristics, can be entered by making both P2.6/SIG
and P2.7/SEC active (see Fig.61). During normal
programming this mode should not be entered therefore
it
is forbidden to make P2.6/SIG and P2.7/SEC HIGH at
the same time
.
15.8.1
M
ASS PROGRAM MODE
The mass program mode can be used to program checker
boards. If this mode is active every internal data latch is
connected to four bit lines and 128 bits can be
programmed in parallel. To write a checker board
0011X0XX has to be loaded in the test register and the
circuit has to be set in the parallel program mode
(P2.2/PGM = 1 and P2.4/GBMbpB = 0). Then data from
address 00H is loaded to address 00 03H down to 00 00H.
For every even word line (A<6> = 0) a program pulse has
to be given at low addresses X0000000 and X0001000.
For the odd lines (A<6> = 1) the pulses have to be applied
to low address x100_0100 and x100_1100. In the user
address space a checker board can be programmed with
320
×
2 = 640 program pulses.
15.9
Signature bytes
Three signature bytes are available to identify the device.
These bytes can be read by doing a verify while the SIG
input (Port 2.6) is active. The contents of the signature
bytes is given in Table 67. Applying a write pulse while the
SIG input is HIGH is forbidden although the contents of the
signature bytes will never be destroyed. The signature
bytes are always readable independent on the security.
Table 67
Addresses and contents of the signature bytes
ADDRESS
CONTENTS
00 30H
00 31H
00 60H
15H
C7H
00H
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