參數(shù)資料
型號(hào)： PCA5007
廠商： NXP Semiconductors N.V.
英文描述： Pager baseband controller
中文描述： 傳呼機(jī)基帶控制器
文件頁(yè)數(shù)： 43/112頁(yè)
文件大?。?/td> 604K
代理商： PCA5007
1998 Oct 07
43
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Table 37
Offset coding (two’s compliment)
6.17.1.2
Clock recovery
The clock recovery regenerates the synchronization clock
using the edges of the incoming NRZ data. When the NRZ
data have no edges for a long time, the synchronization is
maintained by means of the correction information from
the clock correction block.
OFFSET (Hz)
MAGNITUDE
(AVG6 TO AVG0)
9450
9300
...
300
150
0
150
300
...
9300
9450
0111111
0111110
...
0000010
0000001
0000000
1111111
1111110
...
1000001
1000000
The recovered clock is used to sample and shift to left into
an internal register one bit each symbol period in 2-FSK
and two bits in 4-FSK. The symbol period is determined by
bits BD2 to BD0. On the basis of BD bits the demodulator
filter length is also set.
In the clock recovery, a pulse (SYMCLK) is generated
each N-bit, where ‘N’ is defined by means of bits B2 to B0.
This pulse is used to update the DMD3 register. Moreover,
it can be used as an interrupt to the processor through the
IRQ1.3 (symbol interrupt).
The interrupt informs the controller that ‘N’ bits are
available in the DMD3 register.
6.17.2
D
EMODULATOR
C
ONTROL
R
EGISTER
(DMD0)
The demodulator control register DMD0 contains the
control bits for enabling the demodulator function and
setting its mode and data rate.
Table 38
Demodulator Control Register (DMD0, SFR address ECH)
Table 39
Description of the DMD0 bits
7
6
5
4
3
2
1
0
ENB
M
RES
LEV
BD2
BD1
BD0
BIT
SYMBOL
FUNCTION
DMD0.7
DMD0.6
DMD0.5
DMD0.4
DMD0.3
DMD0.2
DMD0.1
DMD0.0
ENB
M
RES
LEV
BD2
BD1
BD0
enable demodulator function
mode selection: logic 0 = I/Q from zero-IF receiver, logic 1 = NRZ data
not used
reserved for future implementation
if set to logic 0 2-FSK demodulation, if set to logic 1 4-FSK demodulation
baud rate setting; see Table 40
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