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參數(shù)資料
| 型號： | P89V664FBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 89/90頁 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 64K 44-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 36 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名稱： | 568-2437 935280835557 P89V664FBC |
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P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
9 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
[1]
Port 1, 2, 3, and 4 enter the bidirectional state (except the I2C pins) with a weak pull-up after reset. In this state, the pins can be used as
inputs or outputs. See the 80C51 Family Hardware Description for details of the port structure.
A reset does not assert the strong pull-up for two clock cycles for these ports which normally occurs when the port transitions from a
LOW to a HIGH state. You must first write a zero, then a logic one to enable the strong pull-up for two clock cycles.
[2]
ALE loading issue: When ALE pin experiences higher loading (>30 pF) during the reset, the microcontroller may accidentally enter into
modes other than normal working mode. The solution is to add a pull-up resistor of 3 k
to 50 k to V
DD, e.g., for ALE pin.
[3]
For 6-clock mode, ALE is emitted at 13 of crystal frequency.
ALE/PROG
27
33
I/O
Address Latch Enable: ALE is the output signal for latching
the low byte of the address during an access to external
memory. This pin is also the programming pulse input (PROG)
for flash programming. Normally the ALE[2] is emitted at a
external timing and clocking. One ALE pulse is skipped during
each access to external data memory. However, if AO is set to
‘1’, ALE is disabled.
XTAL1
15
21
I
Crystal 1: Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.
XTAL2
14
20
O
Crystal 2: Output from the inverting oscillator amplifier.
VDD
38
44
I
Power supply
VSS
16
22
I
Ground
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
TQFP44
PLCC44
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