參數(shù)資料
型號(hào)： P89V664FBC,557
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 53/90頁(yè)
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 64K 44-TQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 800
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 706 (CN2011-ZH PDF)
配用： 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱(chēng)： 568-2437
935280835557
P89V664FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
57 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL
which allows the PCA to stop during Idle mode, WDTE which enables or disables the
Watchdog function on module 4, and ECF which when set causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows.
The watchdog timer function is implemented in module 4 of PCA.
The CCON SFR contains the run control bit for the PCA (CR) and the flags for the PCA
timer (CF) and each module (CCF4:0). To run the PCA the CR bit (CCON.6) must be set
by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the
PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD
register is set. The CF bit can only be cleared by software. Bits 0 through 4 of the CCON
register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are
set by hardware when either a match or a capture occurs. These flags can only be cleared
by software. All the modules share one interrupt vector. The PCA interrupt system is
shown in Figure 27.
Each module in the PCA has a special function register associated with it. These registers
are: CCAPM0 for module 0, CCAPM1 for module 1, etc. The registers contain the bits that
control the mode that each module will operate in.
The ECCF bit (from CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module)
enables the CCFn flag in the CCON SFR to generate an interrupt when a match or
compare occurs in the associated module (see Figure 27).
PWM (CCAPMn.1) enables the pulse width modulation mode.
The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to
toggle when there is a match between the PCA counter and the module’s
capture/compare register.
The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to
be set when there is a match between the PCA counter and the module’s
capture/compare register.
Fig 26. PCA
MODULE0
PCA TIMER/COUNTER
P1[3]/CEX0
MODULE1
P1[4]/CEX1
MODULE2
P1[5]/CEX2
MODULE3
P1[6]/CEX3
MODULE4
P1[7]/CEX4
time base for PCA modules
Module functions:
- 16-bit capture
- 16-bit timer
- 16-bit high speed output
- 8-bit PWM
- watchdog timer (module 4 only)
16 bits
002aab913
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