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參數(shù)資料
| 型號： | P89V664FBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 10/90頁 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 64K 44-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 36 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名稱： | 568-2437 935280835557 P89V664FBC |
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P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
18 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.3 Flash memory
6.3.1 Flash organization
The P89V660/662/664 program memory consists of a 16/32/64 kB block for user code.
The flash can be read or written in bytes and can be erased in 128 pages. A chip erase
function will erase the entire user code memory and its associated security bits. There are
three methods of erasing or programming the flash memory that may be used. First, the
flash may be programmed or erased in the end-user application by calling LOW-state
routines through a common IAP entry point. Second, the on-chip ISP bootloader may be
invoked. This ISP bootloader will, in turn, call LOW-state routines through the same
common entry point that can be used by the end-user application. Third, the flash may be
programmed or erased using the parallel method by using a commercially available
EPROM programmer which supports this device.
6.3.2 Features
Flash internal program memory with 128-byte page erase.
Internal Boot block, containing LOW-state IAP routines available to user code.
Boot vector allows user-provided flash loader code to reside anywhere in the flash
memory space, providing flexibility to the user.
Default loader providing ISP via the serial port, located in upper end of program
memory.
Programming and erase over the full operating voltage range.
Read/Programming/Erase using ISP/IAP.
Programming with industry-standard commercial programmers.
10000 typical erase/program cycles for each byte.
100 year minimum data retention.
Fig 6.
Power-on reset circuit
002aaa543
VDD
8.2 k
Ω
RST
XTAL2
XTAL1
C1
C2
10
μF
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