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| 型號(hào)： | P89V664FBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 44/90頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 64K 44-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 36 |
| 程序存儲(chǔ)器容量： | 64KB（64K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名稱： | 568-2437 935280835557 P89V664FBC |
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P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
49 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.7.1 Mode 0
Serial data enters and exits through RXD and TXD outputs the shift clock. Only 8 bits are
transmitted or received, LSB first. The baud rate is fixed at 16 of the CPU clock frequency.
UART configured to operate in this mode outputs serial clock on TXD line no matter
whether it sends or receives data on RXD line.
6.7.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 12 overflow rate.
6.7.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logical 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or (e.g. the
parity bit (P, in the PSW) could be moved into TB8). When data is received, the 9th data
bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The
baud rate is programmable to either 116 or 132 of the CPU clock frequency, as determined
by the SMOD1 bit in PCON.
6.7.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3
is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is
variable and is determined by the Timer 12 overflow rate.
Table 37.
SCON - Serial port control register (address 98H) bit allocation
Bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
Table 38.
SCON - Serial port control register (address 98H) bit description
Bit
Symbol
Description
7
SM0/FE
The usage of this bit is determined by SMOD0 in the PCON register. If
SMOD0 = 0, this bit is SM0, which with SM1, defines the serial port
mode. If SMOD0 = 1, this bit is FE (Framing Error). FE is set by the
receiver when an invalid stop bit is detected. Once set, this bit cannot
be cleared by valid frames but can only be cleared by software. (Note:
It is recommended to set up UART mode bits SM0 and SM1 before
setting SMOD0 to ‘1’.)
6
SM1
With SM0, defines the serial port mode (see Table 39 below).
5
SM2
Enables the multiprocessor communication feature in Modes 2 and 3.
In Mode 2 or 3, if SM2 is set to ‘1’, then Rl will not be activated if the
received 9th data bit (RB8) is ‘0’. In Mode 1, if SM2 = 1 then RI will not
be activated if a valid stop bit was not received. In Mode 0, SM2
should be ‘0’.
4
REN
Enables serial reception. Set by software to enable reception. Clear by
software to disable reception.
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