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參數資料
| 型號： | P89V664FBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 35/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 64K 44-TQFP |
| 產品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數： | 36 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名稱： | 568-2437 935280835557 P89V664FBC |
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P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
40 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.5.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a fixed divide-by-32 prescaler. Figure 14 shows Mode 0 operation.
1
0
2
8-bit auto-reload Timer/Counter ‘THx’ holds a value
which is to be reloaded into ‘TLx’ each time it
overflows.
1
3
(Timer 0) TL0 is an 8-bit Timer/Counter controlled
by the standard Timer 0 control bits. TH0 is an 8-bit
timer only controlled by Timer 1 control bits.
1
3
(Timer 1) Timer/Counter 1 stopped.
Table 29.
TCON - Timer/Counter control register (address 88H) bit allocation
Bit addressable; Reset value: 0000 0000B; Reset source(s): any reset
Bit
7
6
5
4
3
2
1
0
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 30.
TCON - Timer/Counter control register (address 88H) bit description
Bit
Symbol
Description
7
TF1
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when the processor vectors to Timer 1 Interrupt
routine, or by software.
6
TR1
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter
1 on/off.
5
TF0
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when the processor vectors to Timer 0 Interrupt
routine, or by software.
4
TR0
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter
0 on/off.
3
IE1
Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge/LOW-state is detected. Cleared by hardware when the interrupt
is processed, or by software.
2
IT1
Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/LOW-state that triggers external interrupt 1.
1
IE0
Interrupt 0 Edge flag. Set by hardware when external interrupt 0
edge/LOW-state is detected. Cleared by hardware when the interrupt
is processed, or by software.
0
IT0
Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/LOW-state that triggers external interrupt 0.
Table 28.
TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating
mode …continued
M1
M0
Operating mode
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