參數(shù)資料
型號： P89V664FBC,557
廠商： NXP Semiconductors
文件頁數(shù)： 22/90頁
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 64K 44-TQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 800
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 706 (CN2011-ZH PDF)
配用： 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱： 568-2437
935280835557
P89V664FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
29 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
The I2C-bus will enter Master Transmitter mode by setting the STA bit. The I2C-bus logic
will send the START condition as soon as the bus is free. After the START condition is
transmitted, the SI bit is set, and the status code in S1STA should be 08H. This status
code must be used to vector to an interrupt service routine where the user should load the
slave address to S1DAT and data direction bit (SLA+W). The SI bit must be cleared
before the data transfer can continue.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes are 18H, 20H, or
38H for the master mode or 68H, 78H, or 0B0H if the slave mode was enabled (setting
AA = Logic 1). The appropriate action to be taken for each of these status codes is shown
6.4.5.2
Master receiver mode
In the Master Receiver mode, data is received from a slave transmitter. The transfer
started in the same manner as in the Master Transmitter mode. When the START
condition has been transmitted, the interrupt service routine must load the slave address
and the data direction bit to I2C-bus Data Register (S1DAT). The SI bit must be cleared
before the data transfer can continue.
When the slave address and data direction bit have been transmitted and an
acknowledge bit has been received, the SI bit is set, and the Status Register will show the
status code. For master mode, the possible status codes are 40H, 48H, or 38H. For slave
mode, the possible status codes are 68H, 78H, or B0H. Refer to Table 24 for details.
After a repeated START condition, I2C-bus may switch to the Master Transmitter mode.
Fig 8.
Format in the Master Transmitter mode
S
R/W
A
DATA
data transferred
(n Bytes + acknowledge)
A
A/A
P
slave address
logic 0 = write
logic 1 = read
from master to slave
from slave to master
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
002aaa929
Fig 9.
Format of Master Receiver mode
S
R
A
slave address
logic 0 = write
logic 1 = read
from master to slave
from slave to master
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
002aaa930
DATA
data transferred
(n Bytes + acknowledge)
A
P
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