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參數(shù)資料
| 型號： | P89V664FBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 55/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 64K 44-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 36 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名稱： | 568-2437 935280835557 P89V664FBC |
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P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
59 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
Table 46.
CMOD - PCA counter mode register (address C1H) bit description
Bit
Symbol
Description
7
CIDL
Counter Idle Control: CIDL = 0 programs the PCA Counter to continue
functioning during Idle mode. CIDL = 1 programs it to be gated off
during idle.
6
WDTE
WatchDog Timer Enable: WDTE = 0 disables watchdog timer function
on module 4. WDTE = 1 enables it.
5 to 3
-
Reserved for future use. Should be set to ‘0’ by user programs.
2 to 1
CPS1,
CPS0
PCA Count Pulse Select (see Table 47 below).
0
ECF
PCA Enable Counter Overflow Interrupt: ECF = 1 enables CF bit in
CCON to generate an interrupt. ECF = 0 disables that function.
Table 47.
CMOD - PCA counter mode register (address C1H) count pulse select
CPS1
CPS0
Select PCA input
0
0 Internal clock, fosc /6
0
1
1 Internal clock, fosc /6
1
0
2 Timer 0 overflow
1
3 External clock at ECI/P1[2] pin (max rate = fosc /4)
Table 48.
CCON - PCA counter control register (address 0C0H) bit allocation
Bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
0
Symbol
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
Table 49.
CCON - PCA counter control register (address 0C0H) bit description
Bit
Symbol
Description
7
CF
PCA Counter Overflow Flag. Set by hardware when the counter rolls
over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by
either hardware or software but can only be cleared by software.
6
CR
PCA Counter Run Control Bit. Set by software to turn the PCA counter
on. Must be cleared by software to turn the PCA counter off.
5
-
Reserved for future use. Should be set to ‘0’ by user programs.
4
CCF4
PCA Module 4 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
3
CCF3
PCA Module 3 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
2
CCF2
PCA Module 2 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
1
CCF1
PCA Module 1 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
0
CCF0
PCA Module 0 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
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