參數(shù)資料
型號： P89V664FBC,557
廠商： NXP Semiconductors
文件頁數(shù)： 52/90頁
文件大小： 0K
描述： IC 80C51 MCU FLASH 64K 44-TQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 800
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 706 (CN2011-ZH PDF)
配用： 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱： 568-2437
935280835557
P89V664FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
56 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.9 Watchdog timer
The WDT is intended as a recovery method in situations where the CPU may be
subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog
Timer Reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, the user
must write 01EH and 0E1H, in sequence, to the WDTRST SFR. When the WDT is
enabled, it will increment every machine cycle while the oscillator is running and there is
no way to disable the WDT, except through a reset (either hardware reset or a WDT
overflow reset). When the WDT overflows, it will drive an output reset HIGH pulse at the
RST pin.
When the WDT is enabled (and thus running) the user needs to reset it by writing 01EH
and 0E1H, in sequence, to the WDTRST SFR to avoid WDT overflow. The 14-bit counter
reaches overflow when it reaches 16383 (3FFFH) and this will reset the device.
The WDT’s counter cannot be read or written. When the WDT overflows it will generate a
output pulse at the reset pin with a duration of 98 oscillator periods in 6 clock mode or 196
oscillator periods in 12 clock mode.
6.10 PCA
The PCA includes a special 16-bit Timer that has five 16-bit capture/compare modules
associated with it. Each of the modules can be programmed to operate in one of four
modes: rising and/or falling edge capture, software timer, high-speed output, or pulse
width modulator. Each module has a pin associated with it. Module 0 is connected to
CEX0, module 1 to CEX1, etc. Registers CH and CL contain current value of the free
running up counting 16-bit PCA timer. The PCA timer is a common time base for all five
modules and can be programmed to run at: 16 the oscillator frequency, 12 the oscillator
frequency, the Timer 0 overflow, or the input on the ECI pin (P1[2]). The timer count
source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table 45 and
Fig 25. SPI transfer format with CPHA = 1
002aaa530
MSB
S
PICLK cycle #
(for reference)
S
PICLK (CPOL = 0)
S
PICLK (CPOL = 1)
MOSI
(from master)
MISO
(from slave)
SS (to slave)
6
12
3
4
5
6
7
8
5
MSB
6
5
4
3
2
1
LSB
4
3
2
1
LSB
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