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參數(shù)資料
| 型號： | P89V664FBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 31/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 64K 44-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 36 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名稱： | 568-2437 935280835557 P89V664FBC |
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P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
37 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
A0H
A STOP condition
or repeated
START condition
has been received
while still
addressed as
SLA/REC or
SLA/TRX.
No S1DAT action
0
000Switched to not addressed SLA
mode; no recognition of own SLA or
General call address.
no S1DAT action
0
001Switched to not addressed SLA
mode; Own slave address will be
recognized; General call address
will be recognized if S1ADR.0 = 1.
no S1DAT action
1
000Switched to not addressed SLA
mode; no recognition of own SLA or
General call address. A START
condition will be transmitted when
the bus becomes free.
no S1DAT action
1
001Switched to not addressed SLA
mode; Own slave address will be
recognized; General call address
will be recognized if S1ADR.0 = 1. A
START condition will be transmitted
when the bus becomes free.
Table 24.
Slave Receiver mode …continued
Status code
(S1STA)
Status of the
I2C-bus
hardware
Application software response
Next action taken by I2C-bus
hardware
to/from S1DAT
to S1CON
STA
STO
SI
AA
Table 25.
Slave transmitter mode
Status code
(S1STA)
Status of the
I2C-bus
hardware
Application software response
Next action taken by I2C-bus
hardware
to/from S1DAT
to S1CON
STA
STO
SI
AA
A8H
Own SLA+R has
been received;
ACK has been
returned.
Load data byte or
x
0
Last data byte will be transmitted
and ACK bit will be received.
load data byte
x
0
1
Data byte will be transmitted; ACK
will be received.
B0H
Arbitration lost in
SLA+R/W as
master; Own
SLA+R has been
received, ACK
has been
returned.
Load data byte or
x
0
Last data byte will be transmitted
and ACK bit will be received.
load data byte
x
0
1
Data byte will be transmitted; ACK
bit will be received.
B8H
Data byte in
S1DAT has been
transmitted; ACK
has been
received.
Load data byte or
x
0
Last data byte will be transmitted
and ACK bit will be received
load data byte
x
0
1
Data byte will be transmitted; ACK
will be received.
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