參數(shù)資料
型號(hào)： P89V664FBC,557
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 6/90頁(yè)
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 64K 44-TQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 800
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 706 (CN2011-ZH PDF)
配用： 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱： 568-2437
935280835557
P89V664FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
14 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.2 Memory organization
The various P89V660/662/664 memory spaces are as follows:
DATA
128 B of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
IDATA
Indirect Data. 256 B of internal data memory space (00H:FFH) accessed via indirect
addressing using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area. This area includes the DATA area and the 128 B immediately
above it.
SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
XDATA
‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space
addressed via the MOVX instruction using the DPTR, R0, or R1. The
P89V660/662/664 have 256/768/1792 B of on-chip XDATA memory.
CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89V660/662/664 have 16/32/64 kB of on-chip Code memory.
6.2.1 Expanded data RAM addressing
The P89V660/662/664 have 512 B/1 kB/2 kB of RAM. See Figure 4.
To access the expanded RAM, the EXTRAM bit must be set and MOVX instructions must
be used. The extra memory is physically located on the chip and logically occupies the
first bytes of external memory (addresses 000H to 0FFH/2FFH/6FFH).
When EXTRAM = 1, the expanded RAM is indirectly addressed using the MOVX
instruction in combination with any of the registers R0, R1 of the selected bank or DPTR.
Accessing the expanded RAM does not affect ports P0, P3[6] (WR), P3[7] (RD), or P2.
With EXTRAM = 1, the expanded RAM can be accessed as in the following example.
Expanded RAM Access (Indirect Addressing only):
MOVX@DPTR, A; DPTR contains 0A0H
The DPTR points to location 0A0H and the data in the accumulator is written to address
0A0H of the expanded RAM rather than off-chip external memory. Access to EXTRAM
addresses that are not present on the device (above 0FFH for the 89V660, above 2FFH
Table 5.
AUXR - Auxiliary register (address 8EH) bit allocation
Not bit addressable; Reset value 00H
Bit
7
6
5
4
3
2
1
0
Symbol
--
----
EXTRAM
AO
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