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參數(shù)資料
| 型號： | P89V664FBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 70/90頁 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 64K 44-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 36 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名稱： | 568-2437 935280835557 P89V664FBC |
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P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
72 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
[1]
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
[2]
Under steady state (non-transient) conditions, IOL must be externally limited as follows:
a) Maximum IOL per 8-bit port: 26 mA
b) Maximum IOL total for all outputs: 71 mA
c) If IOL exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
[3]
Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and Ports 1 and 3. The noise due
to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to
qualify ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger STROBE input.
[4]
Load capacitance for Port 0, ALE and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
[5]
Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VDD 0.7 specification when
the address bits are stabilizing.
[6]
Pins of Ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VI is approximately 2 V.
[7]
Pin capacitance is characterized but not tested. EA = 25 pF (max).
ITHL
HIGH-LOW transition current
VI = 2 V, ports 1, 2, 3, 4
[6] --
650
A
ILI
input leakage current
0.45 V < VI <VDD 0.3 V,
port 0
--
10
A
0V<VI <6V,
0V<VDD< 5.5 V, SCL, SDA
--
10
A
Rpd
pull-down resistance
on pin RST
40
-
225
k
Ciss
input capacitance
@ 1 MHz, Tamb =25 C,
VI =0V
[7] -
-
15
pF
IDD(oper)
operating supply current
fosc =12 MHz
-
11.5
mA
fosc =40 MHz
-
50
mA
Programming and erase
mode
--
70
mA
IDD(idle)
Idle mode supply current
fosc =12 MHz
-
8.5
mA
fosc =40 MHz
-
42
mA
IDD(pd)
Power-down mode supply
current
minimum VDD =2V
-
90
A
Table 70.
Static characteristics …continued
Tamb = 40 Cto+85 C; VDD = 4.5 V to 5.5 V; VSS =0V
Symbol
Parameter
Conditions
Min
Typ Max
Unit
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