參數(shù)資料
型號(hào)： P89V664FBC,557
廠商： NXP Semiconductors
文件頁數(shù)： 50/90頁
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 64K 44-TQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 800
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 706 (CN2011-ZH PDF)
配用： 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱： 568-2437
935280835557
P89V664FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
54 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
SPICLK pin is the clock output and input for the master and slave modes, respectively.
The SPI clock generator will start following a write to the master devices SPI data register.
The written data is then shifted out of the MOSI pin on the master device into the MOSI
pin of the slave device. Following a complete transmission of one byte of data, the SPI
clock generator is stopped and the SPIF flag is set. An SPI interrupt request will be
generated if the SPI Interrupt Enable bit (SPIE) and the SPI interrupt enable bit, ES3, are
both set.
An external master drives the Slave Select input pin, SS LOW to select the SPI module as
a slave. If SS has not been driven LOW, then the slave SPI unit is not active and the MOSI
pin can also be used as an input port pin.
CPHA and CPOL control the phase and polarity of the SPI clock. Figure 24 and Figure 25
show the four possible combinations of these two bits.
Fig 23. SPI master-slave interconnection
002aaa528
8-BIT SHIFT REGISTER
MSB master LSB
SPI
CLOCK GENERATOR
MISO
MOSI
SPICLK
SS
8-BIT SHIFT REGISTER
MSB slave LSB
VSS
VDD
Table 40.
SPCR - SPI control register (address D5H) bit allocation
Bit addressable; Reset source(s): any reset; Reset value: 0000 0000B
Bit
7
6
5
4
3
2
1
0
Symbol
SPIE
SPEN
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
Table 41.
SPCR - SPI control register (address D5H) bit description
Bit
Symbol
Description
7
SPIE
If both SPIE and ES3 are set to one, SPI interrupts are enabled.
6
SPEN
SPI enable bit. When set enables SPI.
5
DORD
Data transmission order. 0 = MSB first; 1 = LSB first in data
transmission.
4
MSTR
Master/slave select. 1 = master mode, 0 = slave mode.
3
CPOL
Clock polarity. 1 = SPICLK is high when idle (active LOW),
0 = SPICLK is low when idle (active HIGH).
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