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參數(shù)資料
| 型號： | OXCB950 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance UART Cardbus / PCI interface |
| 中文描述： | 綜合高性能的UART Cardbus / PCI接口 |
| 文件頁數(shù)： | 59/68頁 |
| 文件大?。?/td> | 409K |
| 代理商： | OXCB950 |
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Now that the target has signalled that the clock is to be
maintained, the target's drive on the CCLKRUN#line must
be maintained for 2 clocks during which the host will begin
to drive the line also. Since the CCLKRUN#is also the data
to the 2-bit shift register then, when the CCLKRUN#is
driven by the control circuitry, it will take 2 clock cycles for
the new clock run status to propagate through the logic to
turn off the transistor. During this period, the host will have
detected the assertion of the CCLKRUN#by the target and
will also begin to assert the CLKRUN#line, so that when
the clock control's transistor is turned off, the CCLKRUN#
will be held in the asserted state by the host thereby
keeping the transistor off. The transistor will remain off until
the host next attempts to negate the CCLKRUN#line to
indicate a clock stop and is prevented fromdoing so by the
clock control logic.
For the condition when the device driver needs to place the
oxcb950 into a low powerstate, and the clock control logic
Data Sheet Revision 1.0 PRELIMINARY
Page 59
OXCB950
OXFORD SEMICONDUCTOR LTD.
is not required, then the device driver will assign the MIO0
pin to a logic 0 that disables the clock control circuitry and
forces the clockrun transistor to the off state. For this
condition, when the host negates the CCLKRUN#line it
does not see the CCLKRUN#being asserted by the target
(as the circuitry has been disabled) and the clock is
stopped by the host after the relevant number of clocks
fromthe negation.
Since the UART functionality within the oxcb950 device is
not dependant upon the CCLK line for interrupt generation,
then any activity within the UART that results in an interrupt
will be conveyed to the cardbus interface asynchronously.
This will result in the CCLKRUN#being asserted by the
host (and thus enabling the clock CCLK) and control will be
handed to the device driver that will re-enable the clock
control circuitry to prevent the clock fromstopping until all
tasks have been completed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OXFW900 | IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW900-TQ-A | IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW911 | IEEE1394 to ATA/ATAPI Native Bridge |
| OXFW911-TQ-A | IEEE1394 to ATA/ATAPI Native Bridge |
| OZ6812 | ACPI CardBus Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OXCB950-TQAG | 功能描述:外圍驅(qū)動器與原件 - PCI 32 bit PC Card bridge to serial prt RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| OXCB950-TQC60-A | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance UART Cardbus / 3.3v PCI interface |
| OXCF950 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:low cost asynchronous 16-bit PC card or Compact Flash UART device |
| OXCF950_06 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:low cost asynchronous 16-bit PC card or Compact Flash UART device |
| OXCF950B | 制造商:PLX 制造商全稱:PLX 功能描述:16-bit PC card/CF+ bridge to serial port |
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