參數(shù)資料
型號(hào)： OXCB950
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated High Performance UART Cardbus / PCI interface
中文描述： 綜合高性能的UART Cardbus / PCI接口
文件頁(yè)數(shù)： 18/68頁(yè)
文件大?。?/td> 409K
代理商： OXCB950
Data Sheet Revision 1.1
Page 18
OXCB950
OXFORD SEMICONDUCTOR LTD.
Bits
6
Description
MIO0 Power Down Filter Control
:
A ‘1’ enables the MIO0 pin to invoke a powerdown request via the power
down filter (if the filter is enabled). State of MIO0 that causes the
powerdown request is governed by the controls MIC[1:0).
MIO1 Power Down Filter Control
:
A ‘1’ enables the MIO1 pin to invoke a powerdown request via the power
down filter (if the filter is enabled). State of MIO1 that causes the
powerdown request is governed by the controls MIC[3:2).
Reserved
Read/Write
EEPROM
W
Reset
0
PCI
RW
7
W
RW
0
31:8
-
R
00
6.4.3
The internal UART’s FIFO levels (both on the transmtter and receiver) and general interrupt source register, is mrrored
(shadowed) in the local configuration registers as follows
Bits
Description
7:0
UART Receiver FIFO Level (RFL[7:0])
15:8
UART Transmtter FIFO Level (TFL[7:0])
21:16
UART Interrupt Source Register (ISR[5:0])
26:22
Reserved
27
UART Good-Data Status
31:28
Reserved
Good-Data status for the internal UART is set when all of the following conditions are met:
ISR reads a level0 (no-interrupt pending), a level 2a (receiver data available, a level 2b (receiver time-out) or a level 3
(transmtter THR empty) interrupt
LSR[7] is clear so there is no parity error, framng error or break in the FIFO
LSR[1] is clear so no over-run error has occurred
If the device driver software reads the receiver FIFO levels fromthis register, then if Good-Data status is set, the driver can
remove the number of bytes indicated by the FIFO level without the need to read the line status register. This feature enhances
the driver efficiency.
If the Good-Data status bit is
not
set, then the software driver should examne the ISR bits. If the ISR indicates a level 4 or higher
interrupt, the interrupt is due to a change in the state of modemlines or detection of flow control characters. The device driver-
software should then take appropriate measures as would in any other 550/950 driver. When ISR indicates a level 1 (receiver
status) interrupt then the driver can examne the Line Status Register (LSR) of the relevant channel. Since reading the LSR
clears LSR[7], the device driver-software should either flush or empty the contents of the receiver FIFO, otherwise the Good-
Data status will no longer be valid.
UART Mrror Register ‘UMR’ (Offset 0x08):
Read/Write
EEPROM
-
-
-
-
-
-
Reset
00h
00h
01h
00h
1h
0h
PCI
R
R
R
R
R
R
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OXCB950-TQAG 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32 bit PC Card bridge to serial prt RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
OXCB950-TQC60-A 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance UART Cardbus / 3.3v PCI interface
OXCF950 制造商:OXFORD 制造商全稱:OXFORD 功能描述:low cost asynchronous 16-bit PC card or Compact Flash UART device
OXCF950_06 制造商:OXFORD 制造商全稱:OXFORD 功能描述:low cost asynchronous 16-bit PC card or Compact Flash UART device
OXCF950B 制造商:PLX 制造商全稱:PLX 功能描述:16-bit PC card/CF+ bridge to serial port
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