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參數(shù)資料
| 型號(hào)： | ORT42G5-EV |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 95/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ORCA® 4 系列 |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | ORT42G5 |
| 所含物品： | 板，線纜，電源 |
| 其它名稱： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
77
High Speed Data Receiver
Table 35 species receiver parameters measured on devices with worst case process parameters and over the full
range of operation conditions.
Table 35. External Data Input Specications
Input Data Jitter Tolerance
A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan-
dards have recognized the dependency on jitter type and have recently modified specifications to indicate toler-
ance levels for different jitter types as they relate to specific protocols (e.g XAUI, FC, Infiniband etc.). Sinusoidal
jitter is considered to be a worst case jitter type. Table 36 shows receiver specifications with 10 MHz sinusoidal jit-
ter injection. XAUI specic jitter tolerance measurements were measured in a separate experiment detailed in tech-
nical note TN1032, SERDES Test Chip Jitter, and are not reected in these results.
Table 36. Receiver Sinusoidal Jitter Tolerance Specications
Parameter
Conditions
Min.
Typ.
Max.
Units
Input Data
Stream of Nontransitions
8b/10b encode/decode off
—
72
Bits
Sensitivity (differential), worst-case
1
3.125 Gbps
80
—
mVp-p
Input Levels
2
—
VSS - 0.3
—
VDD_ANA + 0.3
V
Internal Buffer Resistance (Each input to VDDIB)
—
40
50
60
Ω
PLL Lock Time
3
—
Note 2
—
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0
oC to 85oC, 1.425V to 1.575V sup-
ply.
2. Input level min + (input peak to peak swing)/2 ≤ common mode input voltage ≤ input level max - (input peak to peak swing)/2
3. The ORT42G5 and ORT82G5 SERDES receiver performs four levels of synchronization on the incoming serial data stream, providing rst
bit, then byte (character), then channel (32-bit word), and nally optional multi-channel alignment as described in TN1025. The PLL Lock
Time is the time required for the CDR PLL to lock to the transitions in the incoming high-speed serial data stream. If the PLL is unable to
lock to the serial data stream, it instead locks to REFCLK to stabilize the voltage-controlled oscillator (VCO), and periodically switches back
to the serial data stream to again attempt synchronization.
Parameter
Conditions
Max.
Unit
Input Data
Jitter Tolerance @3.125Gbps, Typical
600 mV diff eye
1
0.75
UIP-P
Jitter Tolerance @3.125Gbps, Worst case
600 mV diff eye
1
0.65
UIP-P
Jitter Tolerance @2.5Gbps,Typical
600 mV diff eye
1
0.79
UIP-P
Jitter Tolerance @2.5Gbps, Worst case
600 mV diff eye
1
0.67
UIP-P
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0
oC to 85oC, 1.425V
to 1.575V supply. Jitter measured with a Wavecrest SIA-3000.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT43S | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCBC | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCG | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCO | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCR | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
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