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參數(shù)資料
| 型號： | ORT42G5-EV |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 80/119頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ORCA® 4 系列 |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | ORT42G5 |
| 所含物品： | 板，線纜，電源 |
| 其它名稱： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
63
Control Registers (Read/Write), xx=[AC, AD, BC or BD]
30800 - Ax
30900 - Bx
[0]
—
00
Reserved for future use
[1]
—
Reserved for future use
[2]
ENBYSYNC_xC
ENBYSYNC_xC= 1 Enables Receiver Byte Synchronization for Channel
xC. ENBYSYNC_xC = 0 on device reset.
[3]
ENBYSYNC_xD
ENBYSYNC_xD = 1 Enables Receiver Byte Synchronization for Channel
xA. ENBYSYNC_xD = 0 on device reset.
[4]
—
Reserved for future use
[5]
—
Reserved for future use
[6]
LCKREFN_xC
LCKREFN_xC = 0 Locks the receiver PLL to reference clock for Channel
xC.
LCKREFN_xC =1 = Locks the receiver to data for Channel xx.
NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0.
LCKREFN_xC = 0 on device reset.
[7]
LCKREFN_xD
LCKREFN_xD = 0 Locks the receiver PLL to reference clock for Channel
xD.
LCKREFN_xD =1 = Locks the receiver to data for Channel xA.
NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0.
LCKREFN_xD = 0 on device reset.
30801 - Ax
30901 - Bx
[0]
—
00
Reserved for future use
[1]
—
Reserved for future use
[2]
LOOPENB_xC
Enable Loopback Mode for Channel xC. When LOOPEN_xC=1, the
transmitter high-speed output is looped back to the receiver high-speed
input. This mode is similar to high-speed loopback mode enabled by
TESTMODE_xx except that LOOPEN_xx disables the high-speed serial
output. LOOPEN_xC=0 on device reset.
[3]
LOOPENB_xD
Enable Loopback Mode for Channel xD. When LOOPEN_xD=1, the
transmitter high-speed output is looped back to the receiver high-speed
input. This mode is similar to high-speed loopback mode enabled by
TESTMODE_xx except that LOOPEN_xx disables the high-speed serial
output. LOOPEN_xD=0 on device reset.
[4]
—
Reserved for future use
[5]
—
Reserved for future use
[6]
NOWDALIGN_xC
Word Align Disable Bit. When NOWDALIGN_xC=1, receiver word align-
ment is disabled for Channel xC. NOWDALIGN_xC=0 on device reset.
[7]
NOWDALIGN_xD
Word Align Disable Bit. When NOWDALIGN_xD=1, receiver word align-
ment is disabled for Channel xD. NOWDALIGN_xD=0 on device reset.
Table 28. ORT42G5 Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT43S | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCBC | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCG | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCO | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCR | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
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