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參數(shù)資料
| 型號： | ORT42G5-EV |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 73/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ORCA® 4 系列 |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | ORT42G5 |
| 所含物品： | 板，線纜，電源 |
| 其它名稱： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
57
As mentioned earlier, both sections of a slice can be written independently / simultaneously, due to the indepen-
dent CSW per section.
The same signal illustration above applies to slice B by changing _A to _B.
SDRAM A and SDRAM B in Figure 34 refer to the built-in sections A and B of one EAC RAM slice.
These SDRAMS should not be confused with the FPGA SDRAMS, which are generated through Module Generator
in ispLEVER. The EAC SDRAMs are always built-in to the embedded core section of the ORT82G5/42G5 and their
pins are accessed through the EAC interface. In order for these pins to be available at the interface in the gener-
ated HDL models from ispLEVER, the “Use the Extra Memory in FPSC Core” checkbox needs to be checked in the
customization window (after hitting the "customize" button) in Module Generator, while generating the
ORT82G5/42G5 core HDL. These signals will not otherwise show in the interface model.
Figure 35 and Figure 36 show, per slice, timing diagrams for both write and read accesses. These gures do not
include the _x section, which refers to either slice A or B, even though this is implied. Signal names and functions
are summarized in Table 26 and follow the general ORCA Series 4 naming conventions.
Figure 34. Block Diagram, Embedded Core Memory Slice
4K x 36
D_x[35:0]
Memory Slice
(1 of 2)
2K x 36 Memory
(SRAM A)
(SRAM B)
Write Ports
CKW_x
CSWA_x
CSWB_x
AW_x[10:0]
BYTEWN_x[3]
BW[35,31:24]
BYTEWN_x[2]
BW[34,23:16]
BYTEWN_x[1]
BW[33,15:8]
BYTEWN_x[0]
BW[32,7:0]
Q_x[35:0]
CKR_x
CSR_x
AR_x[10:0]
Read Ports
Side A /
Write Selects
Side B
FPGA
Logic
RAM Block
Read Selects
36
11
36
11
Note: x=[A,B] Slice Identifier
Parity
Data
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