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參數(shù)資料
| 型號： | ORT42G5-EV |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 56/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ORCA® 4 系列 |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | ORT42G5 |
| 所含物品： | 板，線纜，電源 |
| 其它名稱： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
41
Figure 20. Receive Clocking for a Single Block (Similar Connections Would Be Used for Block B)
The receive channel alignment bypass mode allows mixing of half and full line rates among the channels, as shown
in Figure 21. The gure shows channel AC congured in full rate mode at 2.0 Gbps. Channel AD congured in half-
rate mode at 1.0 Gbps. The receive alignment FIFO per channel cannot be used in this mode.
Figure 21. Receive Clocking for Mixed Line Rates
Each SERDES block can also be congured for any line rate (0.6 to 3.7 Gbps), since each block has its own refer-
ence clock input pins.
Multi-Channel Alignment Clocking Strategies for the ORT42G5
The data on the four channels in the ORT42G5 can be independent of each other or can be synchronized in two
different ways. For example, two channels within a SERDES block can be aligned together, channel C and channel
D. Alternatively, all four channels in a SERDES block can be aligned together to form a communication channel
with a bandwidth of 10 Gbps. Individual channels within an alignment group can be disabled (i.e., powered down)
without disrupting other channels. Clocking strategies for these various modes are described in the following para-
graphs.
For dual alignment both channels must be sourced by the same clock. Either RWCKAC or RWCKAD can be con-
nected to RSYS_CLK_A2. A clocking example for dual alignment is shown in Figure 22.
Common Logic, Block A
Channel AC
Channel AD
REFCLK[P:N]_A
2
156.25 MHz
RCK78A
RWCKAC
RWCKAD
RSYS_CLK_A2
FPGA
Logic
Two Channels of
3.125 Gbps
Incoming Serial Data
78.125 MHz
All Recovered
Clocks at
78.125 MHz
Common Logic, Block A
Channel AC
Channel AD
REFCLK[P:N]_A
2
100 MHz
RCK78A
RWCKAC
FPGA
Logic
One Channel of
2.0 Gbps (Full-Rate)
and One Channel of
1.0 Gbps (Half-Rate)
Incoming Serial Data
25 MHz
RWCKAD
25 MHz
or 50 MHz
50 MHz
RSYS_CLK_A2
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