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| 型號(hào)： | ORT42G5-EV |
| 廠(chǎng)商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 90/119頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ORCA® 4 系列 |
| 類(lèi)型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | ORT42G5 |
| 所含物品： | 板，線(xiàn)纜，電源 |
| 其它名稱(chēng)： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
72
30805 - Ax
30905 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
DEMUXWAS_xx
00
Status of Word Alignment. When DEMUX_WAS_xx=1, word alignment is
achieved for Channel xx. DEMUX_WAS_xx=0 on device reset.
[4]xA
[5]xB
[6]xC
[7]xD
CH248_SYNC_xx
Status of Channel Alignment. When CH248_SYNC_xx=1, multi-channel
alignment is achieved for Channel xx. CH248_SYNC_xx=0 on device
reset.
30814 - Ax
30914 - Bx
[0]
xA & AB
[1] xC & xD
SYNC2_[A:B][1:2]
OVFL
00
Multi-Channel Overow Status. When SYNC2_[A:B][1:2]OVFL=1, dual-
channel synchronization FIFO overow has occurred.
SYNC2_[A:B][1:2]OVFL=0 on device reset.
[2]
SYNC4_
[A:B]OVFL
Multi-Channel Overow Status. When SYNC4_[A:B]OVFL=1, quad-
channel synchronization FIFO overow has occurred.
SYNC4_[A:B]OVFL=0 on device reset.
[3]
xA & AB
[4] xC & xD
SYNC2_[A:B][1:2]
OOS
Multi-Channel Out-Of-Sync Status. When SYNC2_[A:B][1:2] OOS=1,
dual-channel synchronization has failed.
SYNC2_[A:B][1:2] OOS=0 on device reset.
[5]
SYNC4_[A:B]_OO
S
Multi-Channel Out-Of-Sync Status. When SYNC4_[A:B]_OOS=1, quad-
channel synchronization has failed.
SYNC4_[A:B]_OOS=0 on device reset.
[6:7]
Reserved for future use.
Common Control Registers (Read/Write)
30A00
[0:1]
TCKSELA
00
Transmit Clock Select. Controls source of 78 MHz TCK78 for SERDES
quad A
00 = Channel AA
10 = Channel AB
01 = Channel AC
11 = Channel AD
[2:3
RCKSELA
Receive Clock Select. Controls source of 78 MHz RCK78 for SEDRES
quad A
00 = Channel AA
10 = Channel AB
01 = Channel AC
11 = Channel AD
[4:5]
TCKSELB
Transmit Clock Select. Controls source of 78 MHz TCK78 for SERDES
quad B
00 = Channel BA
10 = Channel BB
01 = Channel BC
11 = Channel BD
[6:7]
RCKSELB
Receive Clock Select. Controls source of 78 MHz RCK78 for SERDES
quad B
00 = Channel BA
10 = Channel BB
01 = Channel BC
11 = Channel BD
30A01
[0:4]
—
00
Reserved for future use
[5:7]
RX_FIFO_MIN
LSb’s for the threshold for low address in RX_FIFOs. RX_FIFO_MIN, Bit
5 is LSb. Useful values for RX_FIFO_MIN [0:4] are 0 to 17(decimal).
Table 30. ORT82G5 Memory Map (Continued)
(0x)
Absolute
Bit
Name
Reset
Value
(0x)
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT43S | 制造商:BOT 制造商全稱(chēng):Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCBC | 制造商:BOT 制造商全稱(chēng):Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCG | 制造商:BOT 制造商全稱(chēng):Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCO | 制造商:BOT 制造商全稱(chēng):Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCR | 制造商:BOT 制造商全稱(chēng):Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
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