參數(shù)資料
型號： ORT42G5-EV
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 67/119頁
文件大小： 0K
描述： BOARD EVAL ORT42G5/CABLE/ADAPTER
標(biāo)準(zhǔn)包裝： 1
系列： ORCA® 4 系列
類型： FPGA
適用于相關(guān)產(chǎn)品： ORT42G5
所含物品： 板，線纜，電源
其它名稱： ORT42G5EV
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
51
Start Up Sequence for the ORT82G5
The following sequence is required by the ORT82G5 device. For information required for simulation that may be dif-
ferent than this sequence, see the ORT82G5 Design Kit.
1.
Initiate a hardware reset by making PASB_RESETN low. Keep this low during FPGA conguration of the
device. The device will be ready for operation 3 ms after the low to high transition of PASB_RESETN.
2.
Congure the following SERDES internal and external registers. Note that after device initialization, all alarm
and status bits should be read once to clear them. A subsequent read will provide the valid state. Set the fol-
lowing bits in register 30800:
– Bits LCKREFN_[AA:AD] to 1, which implies lock to data.
– Bits ENBYSYNC_[AA:AD] to 1 which enables dynamic alignment to comma.
Set the following bits in register 30801:
– Bits LOOPENB_[AA:AD] to 1 if high-speed serial loopback is desired.
Set the following bits in register 30900:
– Bits LCKREFN_[BA:BD] to 1 which implies lock to data.
– Bits ENBYSYNC_[BA:BD] to 1 which enables dynamic alignment to comma.
Set the following bits in register 30901:
– Bits LOOPENB_[BA:BD] to 1 if high-speed serial loopback is desired.
Set the following bits in registers 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132:
– TXHR set to 1 if TX half-rate is desired.
– 8B10BT set to 1
Set the following bits in registers 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133:
– RXHR Set to 1 if RX half-rate is desired.
– 8B10BR set to 1.
– LINKSM set to 1 if the Fibre Channel state machine is desired.
Assert GSWRST bit by writing two 1’s. Deassert GSWRST bit by writing two 0’s. Wait 3ms. If higher speed
serial loopback has been selected, the receive PLLs will use this time to lock to the new serial data.
Monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130:
– LKI, PLL lock indicator. 1 indicates that PLL has achieved lock.
3. If 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three
times:
– K28.5 D21.4 D21.5 D21.5 or any other idle ordered set (starting with a /comma/) in FC mode.
– /comma/ characters for the XAUI state machine and /A/ characters for word and channel alignment in XAUI
mode.
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