參數(shù)資料
型號(hào)： ORT42G5-EV
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 55/119頁(yè)
文件大小： 0K
描述： BOARD EVAL ORT42G5/CABLE/ADAPTER
標(biāo)準(zhǔn)包裝： 1
系列： ORCA® 4 系列
類(lèi)型： FPGA
適用于相關(guān)產(chǎn)品： ORT42G5
所含物品： 板，線纜，電源
其它名稱： ORT42G5EV
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
40
Figure 18. Transmit Clocking for a Single Block (Similar Connections Would Be Used for Block B)
If the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in
Figure 19 can be used. The gure shows TSYS_CLK_AC being sourced by TCK78A and TSYS_CLK_AD being
sourced by TCK78A/2 (the division is done in FPGA logic). Similar clocking would be used for Block B.
Figure 19. Mixed Rate Transmit Clocking for a Single Block (Similar Connections Would Be Used for Block B)
Receive Clock Source Selection and Recommended Clock Distribution
In the receive path, one clock per block of two channels, called RCK78[A:B], is sent to the FPGA logic. The control
register bits RCKSEL[A:B] is used to select the clock source for these clocks. The selection of the source for
RCK78[A:B] is controlled by this bit as shown in Table 15.
Table 15. RCK78[A:B] Source Selection
In the receive channel alignment bypass mode the data and recovered clocks for the four channels are indepen-
dent. The data for each channel are synchronized to the recovered clock from that channel.
Figure 21 shows the recommended receive clocking for a single block.
RCKSEL[A:B]
Clock Source
0
Channel C
1
Channel D
Common Logic, Block A
Channel AC
Channel AD
REFCLK[P:N]_A
2
156.25 MHz
TCK78A
TSYS_CLK_AC
TSYS_CLK_AD
FPGA
Logic
All Clocks at
78.125 MHz
Two Channels of
3.125 Gbps
Outgoing Serial Data
Common Logic, Block A
Channel AC
Channel AD
REFCLK[P:N]_A
2
100 MHz
TCK78A
TSYS_CLK_AC
TSYS_CLK_AD
FPGA
Logic
One Channel of
2.0 Gbps (Full-Rate)
and One Channel of
1.0 Gbps (Half-Rate)
Outgoing Serial Data
÷ 2
25 MHz
50 MHz
Channel AC Selected
as Clock Source
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