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| 型號(hào)： | ORT42G5-EV |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 59/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ORCA® 4 系列 |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | ORT42G5 |
| 所含物品： | 板，線纜，電源 |
| 其它名稱： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
44
RSYS_CLK_[A:B][1:2]
These clocks are inputs to the SERDES quad block A and B respectively from the FPGA. These are used by each
channel as the read clock to read received data from the alignment FIFO within the embedded core. Clocks
RSYS_CLK_A[1:2] are used by channels in the SERDES quad block A and RSYS_CLK_B[1:2] by channels in the
SERDES quad block B. To guarantee that there is no overow in the alignment FIFO, it is an absolute requirement
that the write and read clocks be frequency locked within 0 ppm. Examples of how to achieve this are shown in the
later section on recommended board-level clocking.
TCK78[A:B]:
This is a muxed output from the core to the FPGA across the core-FPGA interface of one of the 4 transmit SER-
DES clocks per quad operating at up to 92.5 MHz in the embedded core. There is one clock output per SERDES
quad block.
TSYS_CLK[AA,…BD]:
These clocks are inputs to the SERDES quad block A and B respectively from the FPGA. These are used by each
channel to control the timing of the Transmit Data Path. To guarantee correct transmit operation theses clocks must
be frequency locked within 0 ppm to TCK78[A:B].
Transmit and Receive Clock Rates
Table 16 shows the typical relationship between the data rates, the reference clock, the transmit TCK78[A:B] clock
and the receive RCK78[A:B] clock. The selection of full-rate or half-rate for a given reference clock speed is set by
bits in the transmit and receive control registers and can be set per channel.
Table 16. Transmit Data and Clock Rates
Besides taking in a TSYS_CLK_xx from the FPGA logic for each channel, the transmit path logic sends back a
clock of the same frequency, but arbitrary phase. This clock, TCK78[A:B], is derived from the MUX block of one of
the 4 channels in its SERDES quad. The MUX blocks provide the potential source for TCK78[A:B] by a divide-by-4
of the SERDES STBC311xs clock used in synchronizing the transmit data words in the STBC311xx clock domain.
The STBC311xx clocks are internal to the core and are not brought across the core/FPGA interface.
The receiver section receives high-speed serial data at its differential CML input port and sends in to the Clock and
Data Recovery (CDR) block. The CDR block then generates a recovered clock (RWCKxx) and retimes the data.
Thus, the recovered receive clocks are asynchronous between channels.
Transmit Clock Source Selection
The TCKSEL[0:1][A:B] bits select the source channel of TCK78[A:B]. The selection of the source for TCK78[A:B] is
controlled by these bits as shown in Table 17.
Data Rate
Reference Clock
TCK78[A: B] and RCK78[A:B]
Clocks
Rate of Channel
Selected as Clock
Source
0.6 Gbps
60 MHz
15 MHz
Half
1.0 Gbps
100 MHz
25 MHz
Half
1.25 Gbps
125 MHz
31.25 MHz
Half
2.0 Gbps
100 MHz
50 MHz
Full
2.5 Gbps
125 MHz
62.5 MHz
Full
3.125 Gbps
156 MHz
78 MHz
Full
3.7 Gbps
185 MHz
92.5 MHz
Full
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