參數(shù)資料
型號： ORT42G5-EV
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 106/119頁
文件大?。?/td> 0K
描述： BOARD EVAL ORT42G5/CABLE/ADAPTER
標準包裝： 1
系列： ORCA® 4 系列
類型： FPGA
適用于相關產(chǎn)品： ORT42G5
所含物品： 板，線纜，電源
其它名稱： ORT42G5EV
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
87
Package Information
Package Pinouts
Table 43 provides the number of user-programmable I/Os available for each package.
Table 43. I/O Summary
Table 44 and Table 45 provide the package pin and pin function for the ORT42G5 and ORT82G5 FPSC and pack-
ages. The bond pad name is identied in the PIO nomenclature used in the ispLEVER System software design edi-
tor. The Bank column provides information as to which output voltage level bank the given pin is in. The Group
column provides information as to the group of pins the given pin is in. This is used to show which VREF pin is used
to provide the reference voltage for single-ended limited-swing I/Os. If none of these buffer types (such as SSTL,
GTL, HSTL) are used in a given group, then the VREF pin is available as an I/O pin.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specic die, it is indicated as a note in the device column for
the FPGA. The tables provide no information on unused pads.
As shown in the pair columns in Table 38, differential pairs and physical locations are numbered within each bank
(e.g., L19C-A0 is the nineteenth pair in an associated bank). A ‘C’ indicates complementary differential, whereas a
‘T’ indicates true differential. An _A0 indicates the physical location of adjacent balls in either the horizontal or ver-
tical direction. Other physical indicators are as follows:
_A1 indicates one ball between pairs.
_A2 indicates two balls between pairs.
_D0 indicates balls are diagonally adjacent.
_D1 indicates balls are diagonally adjacent, separated by one physical ball.
VREF pins, shown in the Pin Description columns in Table 44 and Table 45, are associated to the bank and group
(e.g., VREF_TL_01 is the VREF for group one of the Top Left (TL) bank.
Device
ORT42G5
ORT82G5
User programmable I/O
204
372
Available programmable differential pair pins
166
330
FPGA conguration pins
7
FPGA dedicated function pins
2
Core function pins
32
71
VDD15
49
63
VDD33
8
10
VDDIO
34
32
VSS
112
91
VDDGB
2
VDDIB
4
8
VDDOB
8
12
VDD_ANA
22
8
No connect
0
2
Total package pins
484
680
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