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| 型號： | ORT42G5-EV |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 18/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ORCA® 4 系列 |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | ORT42G5 |
| 所含物品： | 板，線纜，電源 |
| 其它名稱： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
114
Package Thermal Characteristics Summary
There are three thermal parameters that are in common use: ΘJA, ψJC, and ΘJC. It should be noted that all the
parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials,
the amount of copper in the test board or system board, and system airow.
ΘJA
This is the thermal resistance from junction to ambient (theta-JA, R-theta, etc.):
(1)
where TJ is the junction temperature, TA, is the ambient air temperature, and Q is the chip power.
Experimentally, ΘJA is determined when a special thermal test die is assembled into the package of interest, and
the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The
package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced con-
vection measurements. A controlled amount of power (Q) is dissipated in the test chip’s heater resistor, the chip’s
temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note
that ΘJA is expressed in units of °C/W.
ψJC
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally
used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal
resistance and it is dened by:
(2)
U21
—
VDD15
—
U22
—
VDD15
—
V13
—
VDD15
—
V14
—
VDD15
—
V15
—
VDD15
—
V20
—
VDD15
—
V21
—
VDD15
—
V22
—
VDD15
—
W13
—
VDD15
—
W14
—
VDD15
—
W15
—
VDD15
—
W20
—
VDD15
—
W21
—
VDD15
—
W22
—
VDD15
—
Y16
—
VDD15
—
Y17
—
VDD15
—
Y18
—
VDD15
—
Y19
—
VDD15
—
T32
—
NC
—
W32
—
NC
—
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group
I/O
Pin Description
Additional Function
680-PBGAM
ΘJA =
TJ – TA
Q
ψJC =
TJ – TC
Q
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