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參數(shù)資料
| 型號： | ORT42G5-EV |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 45/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ORCA® 4 系列 |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | ORT42G5 |
| 所含物品： | 板，線纜，電源 |
| 其它名稱： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
31
FMPU_SYNMODE_B = 11111111 (Register Location 30911)
To enable/disable multi-channel alignment of individual channels within a multi-channel alignment group:
FMPU_STR_EN_xx = 1 enabled
FMPU_STR_EN_xx = 0 disabled
(Register Location 30810 and 30910, where xx is one of AC, AD, BC or BD.)
To resynchronize a multichannel alignment group set the following bit to zero, and then set it to one.
FMPU_RESYNC4 for four channels, AC, AD, BC and BD. (Register Location 30A02, bit 2)
FMPU_RESYNC2A for dual channels, AC and AD. (Register Location 30820, bit 5)
FMPU_RESYNC2B for block channels, BC and BD. (Register Location 30920, bit 5)
To resynchronize an independent channel (resetting the write and the read pointer of the FIFO) set the following bit
to zero, and then set it to one.
FMPU_RESYNC1_xx (Register Locations 30820 and 30920, bits 2 and 3, where xx is one of AC, AD, BC or BD).
ORT82G5 Conguration
Register settings for multi-channel alignment are shown in Table 7.
Table 7. Multi-channel Alignment Modes
To align all eight channels:
FMPU_SYNMODE_A[A:D] = 11
FMPU_SYNMODE_B[A:D] = 11
To align all four channels in SERDES A:
FMPU_SYNMODE_A[A:D] = 01
To align two channels in SERDES A:
FMPU_SYNMODE_A[A:B] = 10 for channel AA and AB
FMPU_SYNMODE_A[C:D] = 10 for channel AC and AD
A similar alignment can be dened for SERDES B.
To enable/disable synchronization signal of individual channel within a multi-channel alignment group:
FMPU_STR_EN_xx = 1 enabled
FMPU_STR_EN_xx = 0 disabled
where xx is one of A[A:D] and B[A:D].
To resynchronize a multi-channel alignment group set the following bit to zero, and then set it to one:
FMPU_RESYNC8 for eight channel A[A:D] and B[A:D]
FMPU_RESYNC4A for quad channel A[A:D]
FMPU_RESYNC2A1 for twin channel A[A:B]
Register Bits
FMPU_SYNMODE_xx[0:1]
Mode
00
No multi-channel alignment.
10
Twin channel alignment.
01
Quad channel alignment.
11
Eight channel alignment.
Note: Where xx is one of A[A:D] and B[A:D].
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