參數(shù)資料
型號(hào): ORT42G5-EV
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 79/119頁
文件大?。?/td> 0K
描述: BOARD EVAL ORT42G5/CABLE/ADAPTER
標(biāo)準(zhǔn)包裝: 1
系列: ORCA® 4 系列
類型: FPGA
適用于相關(guān)產(chǎn)品: ORT42G5
所含物品: 板,線纜,電源
其它名稱: ORT42G5EV
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
62
SERDES Common Transmit and Receive Channel Conguration Registers (Read/Write), xx = [AC, AD, BC or BD]
30024 - AC
30034 - AD
30124 - BC
30134 - BD
[0]
Reserved
See
Bit
Desc.
Reserved, must be 0. Set to 0 on device reset.
[1]
MASK_xx
Transmit and Receive Alarm Mask Bit, Channel xx. When MASK_xx = 1,
the transmit and receive alarms of a channel are prevented from gener-
ating an interrupt (i.e., they are masked or disabled). The MASK_xx bit
overrides the individual alarm mask bits in the Alarm Mask Registers.
MASK_xx = 1 on device reset.
[2]
SWRST_xx
Transmit and Receive Software Reset Bit, Channel xx. When
SWRST_ss = 1, this bit provides the same function as the hardware
reset, except that all conguration register settings are unaltered. This is
not a self-clearing bit. Once set, this bit must be manually set and
cleared. SWRST = 0 on device reset.
[3:6] Not used
Not used
[7]
TESTEN_xx
Transmit and Receive Test Enable Bit, Channel xx. When TESTEN_xx =
1, the transmit and receive sections are placed in test mode. The
TestMode_[A:B][4:0] bits in the Global Control Registers specify the par-
ticular test, and must also be set.
Note: When the global test enable bit GTESTEN_[A:B] = 0, the individual
channel test enable bits are used to selectively place a channel in test or
normal mode. When GTESTEN_[A:B] = 1, all channels in a block are set
to test mode regardless of their TESTEN setting. TESTEN_xx = 0 on
device reset.
SERDES Global Control Registers (Read Write) - Act on Both Channels in SERDES Block A or SERDES Block B.
30005 - A
30105 - B
[0]
Reserved
See
Bit
Desc.
Reserved, must be 0. Set to 0 on device reset.
[1]
GMASK_[A:B]
Global Mask. When GMASK_[A:B] = 1, the transmit and receive alarms
of both channels in the SERDES block are prevented from generating an
interrupt (i.e., they are masked or disabled). The GMASK_[A:B] bit over-
rides the individual MASK_xx bits. GMASK_[A:B] = 1 on device reset.
[2]
GSWRST_[A:B]
Software reset bit. The GSWRST_[A:B] bit provides the same function
as the hardware reset for the transmit and receive sections of both chan-
nels, except that the device conguration settings are not affected when
GSWRST_[A:B] is asserted. This is not a self-clearing bit. Once set, this
bit must be manually set and cleared. The GSWRST_[A:B] bit overrides
the individual SWRST_xx bits. GSWRST_[A:B] = 0 on device reset.
[3]
GPWRDNT_[A:B]
Powerdown Transmit Function. When GPWRDNT_[A:B] = 1, sections of
the transmit hardware for both channels are powered down to conserve
power. The GPWRDNT_[A:B] bit overrides the individual PWRDNT_xx
bits. GPWRDNT_[A:B] = 0 on device reset.
[4]
GPWRDNR_[A:B]
Powerdown Receive Function. When GPWRDNR_[A:B] = 1, sections of
the receive hardware for both channels are powered down to conserve
power. The GPWRDNR_[A:B] bit overrides the individual PWRDNR_xx
bits. GPWRDNR_[A:B] = 0 on device reset.
[5]
Reserved
Reserved, 1 on device reset.
[6]
Not used
[7]
GTESTEN_[A:B]
Test Enable Control. When GTESTEN_[A:B] = 1, the transmit and
receive sections of both channels are placed in test mode. The
GTESTEN_[A:B] bit overrides the individual TESTEN_xx bits.
GTESTEN_[A:B] = 0 on device reset.
30006 - A
30106 - B
[0:4] TestMode[A:B]
00
Test Mode - See Test Mode section for settings
[5]
Not used
[6:7] Reserved
Reserved
Table 28. ORT42G5 Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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