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參數(shù)資料
| 型號(hào)： | ORT42G5-EV |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 60/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ORCA® 4 系列 |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | ORT42G5 |
| 所含物品： | 板，線纜，電源 |
| 其它名稱： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
45
Table 17. TCK78[A:B] Source Selection
Recommended Transmit Clock Distribution for the ORT82G5
As an example of the recommended clock distribution approach, TSYS_CLK_A[A:D] can be sourced by TCK78A
as shown in Figure 25 if the transmit line rate are common for all four channels in a quad. Similar clocking would be
used for Quad B.
Figure 25. Transmit Clocking for a Single Block (Similar Connections Would Be Used for Block B)
If the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in
Figure 26 can be used. The gure shows TSYS_CLK_AA and TSYS_CLK_AB being sourced by TCK78A and
TSYS_CLK_AC and TSYS_CLK_AD being sourced by TCK78A/2 (the division is done in FPGA logic). Similar
clocking would be used for Quad B.
TCKSEL0
TCKSEL1
Clock Source
0
Channel A
1
0
Channel B
0
1
Channel C
1
Channel D
Common Logic, Quad A
Channel AA
Channel AB
Channel AD
Channel AC
REFCLK[P:N]_A
2
156.25 MHz
TCK78A
TSYS_CLK_AA
TSYS_CLK_AC
TSYS_CLK_AB
TSYS_CLK_AD
FPGA
Logic
All Clocks at
78.125 MHz
Four Channels of
3.125 Gbps
Outgoing Serial Data
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| ORT43S | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCBC | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCG | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCO | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
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