參數(shù)資料
型號(hào): NAND01GR4B2CZA1E
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 64M X 16 FLASH 1.8V PROM, 25000 ns, PBGA63
封裝: 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, VFBGA-63
文件頁(yè)數(shù): 31/64頁(yè)
文件大小: 632K
代理商: NAND01GR4B2CZA1E
NAND01G-B, NAND02G-B
Data protection
37/64
If the Start Block Address is the same as the End Block Address, only one block is unlocked.
Only one consecutive area of blocks can be unlocked at any one time. It is not possible to
unlock multiple areas.
Figure 16.
Blocks Unlock Operation
1.
Three address cycles are required for 2 Gb devices. 1Gb devices only require two address cycles.
7.3
Blocks Lock-Down
The Lock-Down feature provides an additional level of protection. A Locked-down block
cannot be unlocked by a software command. Locked-Down blocks can only be unlocked by
setting the Write Protect signal to Low for a minimum of 100ns.
Only locked blocks can be locked-down. The command has no affect on unlocked blocks.
Refer to Figure 23: Command Latch AC Waveforms for details on how to issue the
command.
7.4
Block Lock Status
In Block Lock mode (PRL High) the Block Lock Status of each block can be checked by
issuing a Read Block Lock Status command (see Table 10: Commands).
The command consists of:
one bus cycle to give the command code
three bus cycles to give the block address
After this, a read cycle will then output the Block Lock Status on the I/O pins on the falling
edge of Chip Enable or Read Enable, whichever occurs last. Chip Enable or Read Enable
do not need to be toggled to update the status.
The Read Block Lock Status command will not be accepted while the device is busy (RB
Low).
The device will remain in Read Block Lock Status mode until another command is issued.
I/O
WP
Start Block Address, 3 cycles
ai08670
23h
Blocks Unlock
Command
Add1
Add2
Add3
24h
Add1
Add2
Add3
End Block Address, 3 cycles
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