參數(shù)資料
型號(hào): NAND01GR4B2CZA1E
廠商: STMICROELECTRONICS
元件分類(lèi): PROM
英文描述: 64M X 16 FLASH 1.8V PROM, 25000 ns, PBGA63
封裝: 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, VFBGA-63
文件頁(yè)數(shù): 13/64頁(yè)
文件大小: 632K
代理商: NAND01GR4B2CZA1E
Bus operations
NAND01G-B, NAND02G-B
20/64
4.4
Data Output
Data Output bus operations are used to read: the data in the memory array, the Status
Register, the lock status, the Electronic Signature and the Unique Identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low. The data is output sequentially using the Read Enable
signal.
See Figure 26 and Table 25 for details of the timings requirements.
4.5
Write Protect
Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
4.6
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
Bus Operations
Bus Operation
E
AL
CL
R
W
WP
I/O0 - I/O7
I/O8 - I/O15(1)
1. Only for x16 devices.
Command Input
VIL
VIH
Rising
X(2)
2. WP must be VIH when issuing a program or erase command.
Command
X
Address Input
VIL
VIH
VIL
VIH
Rising
X
Address
X
Data Input
VIL
VIH
Rising
VIH
Data Input
Data Output
VIL
Fallin
g
VIH
X
Data Output
Write Protect
X
VIL
XX
Standby
VIH
XX
X
VIL/VD
D
XX
Table 6.
Address Insertion, x8 Devices
Bus Cycle(1)
1.
Any additional address input cycles will be ignored.
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
A7
A6
A5
A4
A3
A2
A1
A0
2nd
VIL
A11
A10
A9
A8
3rd
A19
A18
A17
A16
A15
A14
A13
A12
4th
A27
A26
A25
A24
A23
A22
A21
A20
5th(2)
2.
The fifth cycle is valid for 2Gb devices. A28 is for 2Gb devices only.
VIL
A28
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