
13-14
MPC565/MPC566 Reference Manual
MOTOROLA
Programming the QADC64E Registers
13.2.2 QADC64E Interrupt Register
QADCINT specifies the priority level of QADC64E interrupt requests. The interrupt level
for queue 1 and queue 2 may be different. The interrupt register is read/write accessible in
supervisor data space only. The implemented interrupt register fields can be read and
written, reserved bits read zero and writes have no effect. They are typically written once
when the software initializes the QADC64E, and not changed afterwards.
The QADC64E conditionally generates interrupts to the bus master via the IMB IRQ
signals. When the QADC64E sets a status bit assigned to generate an interrupt, the
QADC64E drives the IRQ bus. The value driven onto IRQ[7:0] represents the interrupt
level assigned to the interrupt source. Under the control of ILBS, each interrupt request
level is driven during the time multiplexed bus during one of four different time slots, with
eight levels communicated per time slot. No hardware priority is assigned to interrupts.
Furthermore, if more than one source on a module requests an interrupt at the same level,
the system software must assign a priority to each source requesting at that level.
Figure 13-7 displays the interrupt levels on IRQ with ILBS.
MSB
0
123
4567
89
10
11
12
13
14
LSB
15
IRL1
IRL2
RESERVED
RESET:
0
0000
00000
0000
Figure 13-6. QADCINT — QADC Interrupt Register0x30 4804
0x30 4C04
Table 13-7. QADCINT Bit Descriptions
Bit(s)
Name
Description
0:4
IRL1
Queue 1 Interrupt Request Level — The IRL1 field establishes the queue 1 interrupt request level.
The 00000 state provides a level 0 interrupt while 11111 provides a level 31 interrupt. All interrupts
are presented on the IMB. Interrupt level priority software determines which level has the highest
priority request.
5:9
IRL2
Queue 2 Interrupt Request Level — The IRL2 field establishes the queue 2 interrupt request level.
The 00000 state provides a level 0 interrupt while 11111 provides a level 31 interrupt. All interrupts
are presented on the IMB. Interrupt level priority software determines which level has the highest
priority request.
10:15
—
Reserved. These bits are used for the IARB (interrupt arbitration ID) field in QADC64E
implementations that use hardware interrupt arbitration. These bits are not used on the
MPC565/MPC566.